View HD404459_5701382.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HD404459 series rev. 6.0 sept. 1998 description the HD404459 series is a member of the 4-bit hmcs400-series microcomputers with large-capacity memory and architecture providing high program productivity. each microcomputer has a 32-khz oscillator for clock, low-voltage (1.8 v) operating mode, and four low-power dissipation modes. the HD404459 series includes three chips: the hd404458 with an 8-kword rom; the HD404459 with a 16-kword rom; and the hd4074459 with a 16-kword prom (ztat tm version). the hd4074459 is a prom version (ztat tm microcomputer). a program can be written to the prom by a prom writer, thus dramatically shortening system development periods and turnaround time (ztat tm versions are 27256-compatible). ztat tm : zero turn around time ztat is a trademark of hitachi, ltd. features 8,192-word 10-bit rom (hd404458) 16,384-word 10-bit rom (HD404459 and hd4074459) 512-digit 4-bit ram (hd404458) 768-digit 4-bit ram (HD404459 and hd4074459) 56 i/o pins, including seven input pins four timer/counters 1-channel 8-bit input capture circuit three timer outputs (including two pwm outputs) two event counter inputs (including one double-edge function) 8-bit clock-synchronous serial interface eight wakeup inputs four-channel voltage comparator (external or internal reference power supply can be selected) built-in oscillators ? main clock: 4-mhz ceramic or crystal oscillator (an external clock is also possible) ? subclock: 32.768-khz crystal
HD404459 series 2 ten interrupt sources ? five by external sources, including two double-edge function ? five by internal sources subroutine stack up to 16 levels, including interrupts four low-power dissipation modes (transition time shortened) ? stop mode ? standby mode ? watch mode ? subactive mode (optional) one external input for transition from stop mode to active mode instruction cycle time ? for hd404458/HD404459: 1, 2, 4, 8 m s (f osc = 4 mhz; 1/4, 1/8, 1/16, 1/32 division ratio) ? for hd4074459: 1, 2, 4, 8 m s (f osc = 4 mhz; 1/4, 1/8, 1/16, 1/32 division ratio; power voltage of 2.7 v or higher) 2, 4, 8, 16 m s (f osc = 2 mhz; 1/4, 1/8, 1/16, 1/32 division ratio; power voltage of 2.2 v or higher) two general operating conditions ? mcu or prom mode for hd4074459 ? mcu mode only for hd404458/HD404459 ordering information type product name model name rom (words) ram (digits) package mask rom hd404458 hd404458h 8,192 512 64-pin plastic qfp (fp-64a) HD404459 HD404459h 16,384 768 64-pin plastic qfp (fp-64a) ztat tm hd4074459 hd4074459h 16,384 768 64-pin plastic qfp (fp-64a)
HD404459 series 3 pin arrangement fp-64a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 r5 3 ( wu 3 ) r5 2 ( wu 2 ) r5 1 ( wu 1 ) r5 0 ( wu 0 ) r4 3 /so r4 2 /si r4 1 / sck r4 0 /evnd r3 3 / evnb r3 2 /tod r3 1 /toc r3 0 /tob r2 3 r2 2 r2 1 r2 0 ra 0 /comp 0 ra 1 /comp 1 ra 2 /comp 2 ra 3 /comp 3 test osc 1 osc 2 gnd x2 x1 reset d 0 d 1 d 2 d 3 4 r9 3 /vc ref r9 2 r9 1 r9 0 r8 3 r8 2 r8 1 r8 0 r7 3 r7 2 r7 1 r7 0 r6 3 ( wu 7 ) r6 2 ( wu 6 ) r6 1 ( wu 5 ) r6 0 ( wu 4 ) d 5 d 6 d 7 d 8 d 9 d 10 d 11 / stopc v cc r0 0 / int 0 r0 1 / int 1 r0 2 /int 2 r0 3 /int 3 r1 0 r1 1 r1 2 r1 3 d
HD404459 series 4 pin description pin number item symbol fp-64a i/o function power supply v cc 24 power voltage gnd 8 ground test test 5 i used for factory testing only: connect this pin to v cc reset reset 11 i resets the mcu oscillator osc 1 6 i input/output pins for the internal oscillator circuit: connect them to a ceramic, crystal, or connect only osc 1 to an external oscillator circuit osc 2 7o x1 10 i used for a 32.768-khz crystal for clock purposes. if not to be used, fix the x1 pin to v cc and leave the x2 pin open. x2 9 o ports d 0 ? 9 12?1 i/o input/output pins addressable by individual bits d 10 , d 11 22, 23 i input pins addressable by individual bits r0 0 ?9 3 25?4 i/o input/output pins addressable in 4-bit units. the r9 3 port is an input-only pin. ra 0 ?a 3 1? i input pins addressable in 4-bit units interrupts int 0 , int 1 , int 2 , int 3 , wu 0 wu 7 25?8, 45?2 i input pins for external interrupts stop clear stopc 23 i input pin for transition from stop mode to active mode serial interface sck 42 i/o serial clock input/output pin si 43 i serial receive data input pin so 44 o serial transmit data output pin timers tob, toc, tod 37?9 o timer output pins evnb , evnd 40, 41 i event count input pins voltage comparator comp 0 comp 3 1? i analog input pins for voltage comparator vc ref 64 i standard voltage pin for inputting the threshold voltage of analog input pins
HD404459 series 5 block diagram system control external interrupt timer a timer b timer c timer d serial interface compa- rator internal data bus internal address bus ram (512 4 bits) (768 4 bits) w (2 bits) x (4 bits) y (4 bits) spx (4 bits) st (1 bit) ca (1 bit) a (4 bits) b (4 bits) sp (10 bits) pc (14 bits) instruction decoder cpu r0 r0 r0 r0 r1 r1 r1 r1 r2 r2 r2 r2 r3 r3 r3 r3 r4 r4 r4 r4 r5 r5 r5 r5 r6 r6 r6 r6 r7 r7 r7 r7 r8 r8 r8 r8 r9 r9 r9 r9 ra ra ra ra reset test stopc osc osc x1 x2 v gnd toc evnd tod int int int int wu 0 to wu 7 vcref comp 0 comp 1 comp 2 comp 3 r0 port r1 port r2 port r3 port r4 port 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 r5 port r6 port r7 port r8 port r9 port ra port si so sck rom (8,192 10 bits) (16,384 10 bits) d port d d d d d d d d d d d d 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 evnb tob spy (4 bits) alu 1 2 cc
HD404459 series 6 memory map rom memory map see the rom memory map of figure 1. vector address area ($0000?000f): reserved for jmpl instructions that branch to the start addresses of the reset and interrupt routines. after mcu reset or an interrupt, program execution continues from the vector address. zero-page subroutine area ($0000?003f): reserved for subroutines. the program branches to a subroutine in this area in response to the cal instruction. pattern area ($0000?0fff): contains rom data that can be referenced with the p instruction. program area ($0000?1fff for hd404458, $0000?3fff for HD404459/hd4074459): used for program coding. vector address zero-page subroutine (64 words) pattern (4,096 words) hd404458 program (8,192 words) HD404459, hd4074459 program (16,384 words) $0000 $000f $0010 $0fff $1000 $1fff $2000 $3fff $003f $0040 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f jmpl instruction (jump to reset, stopc routine) jmpl instruction (jump to int routine) jmpl instruction (jump to timer d routine) jmpl instruction (jump to timer a, int 2 routine) jmpl instruction (jump to timer b, int 3 routine) jmpl instruction (jump to timer c, serial routine) jmpl instruction (jump to wakeup routine) jmpl instruction (jump to int routine) 0 1 figure 1 rom memory map
HD404459 series 7 ram memory map the hd404458 mcu contains a 512-digit 4-bit ram area. the HD404459 and hd4074459 mcus contain 768-digit 4-bit ram areas. both of these ram areas consist of a memory register area, a data area, and a stack area. in addition, an interrupt control bits area, special register area, and register flag area are mapped onto the same ram memory space labeled as the ram-mapped register area. see the ram memory map of figure 2. ram-mapped register area ($000?03f): interrupt control bits area ($000?003) this area is used for interrupt control bits (figure 3). these bits can be accessed only by ram bit manipulation instructions (sem/semd, rem/remd, and tm/tmd). however, note that not all the instructions can be used for each bit. for limitations on using the instructions, refer to figure 4. special function register area ($004?01f, $024?03f) this area is used as mode registers and data registers for external interrupts, serial interface, timer/counters, and as data control registers for i/o ports. see figures 2 and 5. these registers can be classified into three types: write-only (w), read-only (r), and read/write (r/w). ram bit manipulation instructions cannot be used for these registers. register flag area ($020?023) this area is used for the dton, wdon, and other register flags and interrupt control bits (figure 3). these bits can be accessed only by ram bit manipulation instructions (sem/semd, rem/remd, and tm/tmd). however, note that not all the instructions can be used for each bit. for limitations on using the instructions, refer to figure 4. memory register (mr) area ($040?04f): consisting of 16 addresses, this area (mr0?r15) can be accessed by register-register instructions (lamr and xmra). see figure 6. data area ($050?1ff for hd404458, $050?2ff for HD404459/hd4074459) stack area ($3c0?3ff): used for saving the contents of the program counter (pc), status flag (st), and carry flag (ca) at subroutine call (cal or call instruction) and for interrupts. this area can be used as a 16-level nesting subroutine stack in which one level requires four digits. see figure 6 for the data to be saved and the save conditions. the program counter is restored by either the rtn or rtni instruction, but the status and carry flags can only be restored by the rtni instruction. any unused space in this area can be used for data storage.
HD404459 series 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01a $01b $01c $01d $01e $01f $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02a $02b $02c $02d $02e $02f $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03a $03b $03c $03d $03e $03f 10 11 $00a $00b timer read register b lower timer read register b upper (trbl) (trbu) r r timer write register b lower timer write register b upper (twbl) (twbu) w w 14 15 $00e $00f timer read register c lower timer read register c upper (trcl) (trcu) r r timer write register c lower timer write register c upper (twcl) (twcu) w w 17 18 $011 $012 timer read register d lower timer read register d upper (trdl) (trdu) r r timer write register d lower timer write register d upper (twdl) (twdu) w w 0 64 80 512 768 960 $000 $040 $050 $200 $300 $3c0 1023 $3ff * note: * two registers are mapped onto the same address ($00a, $00b, $00e, $00f, $011, and $012). r: w: r/w: read only write only read/write interrupt control bits area port mode register a serial mode register a serial data register lower serial data register upper timer mode register a timer mode register b1 miscellaneous register timer mode register c1 timer mode register d1 timer mode register b2 timer mode register c2 timer mode register d2 comparator control register comparator enable register wakeup select register port mode register b port mode register c detection edge select register 1 detection edge select register 2 serial mode register b system clock select register 1 system clock select register 2 port d 0 to d 3 dcr port d 4 to d 7 dcr port d 8 to d 9 dcr port r 0 dcr port r 1 dcr port r 2 dcr port r 3 dcr port r 4 dcr port r 5 dcr port r 6 dcr port r 7 dcr port r 8 dcr port r 9 dcr (pmra) (smra) (srl) (sru) (tma) (tmb1) (trbl/twbl) (trbu/twbu) (mis) (tmc1) (trcl/twcl) (trcu/twcu) (tmd1) (trdl/twdl) (trdu/twdu) (tmb2) (tmc2) (tmd2) (ccr) (cer) (wsr) (pmrb) (pmrc) (esr1) (esr2) (smrb) (ssr1) (ssr2) (dcd0) (dcd1) (dcd2) (dcr0) (dcr1) (dcr2) (dcr3) (dcr4) (dcr5) (dcr6) (dcr7) (dcr8) (dcr9) w w r/w r/w w w r/w r/w w w r/w r/w w r/w r/w r/w r/w r/w w r/w r w w w w w w w w w w w w w w w w w w w w register flag area not used not used not used ram-mapped register memory register (mr) hd404458 data (432 digits) HD404459, hd4074459 data (688 digits) stack (64 digits) not used not used timer b timer c timer d figure 2 ram memory map
HD404459 series 9 0 1 2 3 bit 3 bit 2 bit 1 bit 0 imtd (im of timer d) iftd (if of timer d) im1 (im of int 1 ) if1 (if of int 1 ) imtb (im of timer b) iftb (if of timer b) imta (im of timer a) ifta (if of timer a) imwu (im of wakeup) imtc (im of timer c) iftc (if of timer c) $000 $001 $002 $003 interrupt control bits area im0 (im of int 0 ) if0 (if of int 0 ) rsp (reset sp bit) ie (interrupt enable flag) 32 33 34 35 icsf (input capture status flag) im3 (im of int 3 ) if3 (if of int 3 ) im2 (im of int 2 ) if2 (if of int 2 ) ims (im of serial) ifs (if of serial) $020 $021 $022 $023 register flag area dton (direct transfer on flag) cmsf (comparator start flag) wdon (watchdog on flag) lson (low speed on flag) icef (input capture error flag) rame (ram enable flag) not used if: im: sp: interrupt request flag interrupt mask stack pointer bit 3 bit 2 bit 1 bit 0 ifwu (if of wakeup) not used not used figure 3 configuration of interrupt control bits and register flag areas ie im lson if icsf icef rame rsp wdon cmsf not used dton sem/semd rem/remd tm/tmd allowed allowed allowed not executed allowed allowed not executed allowed inhibited allowed not executed inhibited allowed inhibited allowed not executed in active mode allowed allowed used in subactive mode not executed not executed inhibited note: wdon is reset by mcu reset or by stopc enable for stop mode cancellation. the rem or remd instuction must not be executed for cmsf during comparator operation. dton is always reset in active mode. if the tm or tmd instruction is executed for the inhibited bits or non-existing bits, the value in st becomes undefined. figure 4 usage limitations of ram bit manipulation instructions
HD404459 series 10 $000 $003 pmra $004 smra $005 srl $006 sru $007 tma $008 tmb1 $009 trbl/twbl $00a trbu/twbu $00b mis $00c tmc1 $00d trcl/twcl$00e trcu/twcu $00f tmd1 $010 trdl/twdl $011 trdu/twdu $012 tmb2 $013 tmc2 $014 tmd2 $015 ccr $016 cer $017 wsr $018 $020 $023 pmrb $024 pmrc $025 esr1 $026 esr2 $027 smrb $028 ssr1 $029 ssr2 $02a dcd0 $02c dcd1 $02d dcd2 $02e dcr0 $030 dcr1 $031 dcr2 $032 dcr3 $033 dcr4 $034 dcr5 $035 dcr6 $036 dcr7 $037 dcr8 $038 dcr9 $039 $03f not used interrupt control bits area r4 2 /si r4 3 /so r4 1 / sck serial transmit clock speed selection serial data register (lower digit) serial data register (upper digit) timer-a/timer-base auto-reload on/off clock source selection (timer a) clock source selection (timer b) timer b register (lower digit) timer b register (upper digit) pull-up mos control auto-reload on/off auto-reload on/off so pmos control interrupt frame period selection clock source selection (timer c) timer c register (lower digit) timer c register (upper digit) clock source selection (timer d) timer d register (lower digit) timer d register (upper digit) timer b output mode selection timer c output mode selection timer d output mode selection internal reference voltage level selection voltage comparison result wu 7 enable wu 6 enable wu 5 to wu 4 enable wu 3 to wu 0 enable r0 3 /int 3 r0 2 /int 2 r0 1 / int 1 r0 0 / int 0 d 11 / stopc r4 0 /evnd r3 3 / evnb int 3 detection edge selection evnd detection edge selection int 2 detection edge selection so output level control in idle states 32-khz oscillation sampling selection serial clock source selection 32-khz oscillation stop 32-khz oscillation division ratio selection osc division ratio selection port d3 dcr port d7 dcr port d2 dcr port d6 dcr port d1 dcr port d5 dcr port d9 dcr port d0 dcr port d4 dcr port d8 dcr port r0 3 dcr port r1 3 dcr port r2 3 dcr port r3 3 dcr port r4 3 dcr port r5 3 dcr port r6 3 dcr port r7 3 dcr port r8 3 dcr port r0 2 dcr port r1 2 dcr port r2 2 dcr port r3 2 dcr port r4 2 dcr port r5 2 dcr port r6 2 dcr port r7 2 dcr port r8 2 dcr port r9 2 dcr port r0 1 dcr port r1 1 dcr port r2 1 dcr port r3 1 dcr port r4 1 dcr port r5 1 dcr port r6 1 dcr port r7 1 dcr port r8 1 dcr port r9 1 dcr port r0 0 dcr port r1 0 dcr port r2 0 dcr port r3 0 dcr port r4 0 dcr port r5 0 dcr port r6 0 dcr port r7 0 dcr port r8 0 dcr port r9 0 dcr not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used reference power supply selection comp 0 to comp 3 selection register flag area bit 3 bit 2 bit 1 bit 0 input capture selection figure 5 special function register area
HD404459 series 11 memory registers 64 65 66 67 68 69 70 71 73 74 75 76 77 78 79 72 $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04a $04b $04c $04d $04e $04f 960 $3c0 1023 $3ff mr(0) mr(1) mr(2) mr(3) mr(4) mr(5) mr(6) mr(7) mr(8) mr(9) level 16 level 15 level 14 level 13 level 12 level 11 level 10 level 9 level 8 level 7 level 6 level 5 level 4 level 3 level 2 level 1 mr(10) mr(11) mr(12) mr(13) mr(14) mr(15) pc pc pc pc pc pc pc pc pc pc pc pc st pc ca pc 10 3 13 9 6 2 12 8 5 1 11 7 4 0 bit 3 bit 2 bit 1 bit 0 $3fc $3fd $3fe $3ff 1020 1021 1022 1023 stack area pc ?c : st: status flag ca: carry flag program counter 13 0 figure 6 configuration of memory registers, stack area, and stack position
HD404459 series 12 functional description registers and flags the mcu has nine registers and two flags for cpu operations (figure 7). 30 30 30 30 30 30 0 0 0 13 95 1 (b) (a) (w) (x) (y) (spx) (spy) (ca) (st) (pc) (sp) 1111 accumulator b register w register x register y register spx register spy register carry status program counter initial value: 0, no r/w stack pointer initial value: $3ff, no r/w 0 0 initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: 1, no r/w figure 7 registers and flags accumulator (a), b register (b): four-bit registers used to hold the results from the arithmetic logic unit (alu) and transfer data between memory, i/o, and other registers. w register (w), x register (x), y register (y): two-bit (w) and four-bit (x and y) registers used for indirect ram addressing. the y register is also used for d-port addressing.
HD404459 series 13 spx register (spx), spy register (spy): four-bit registers used to supplement the x and y registers. carry flag (ca): one-bit flag that stores any alu overflow generated by an arithmetic operation. ca is affected by the sec, rec, rotl, and rotr instructions. a carry is pushed onto the stack during an interrupt and popped from the stack by the rtni instruction?ut not by the rtn instruction. status flag (st): one-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the alu, or result of a bit test. st is used as a branch condition of the br, brl, cal, and call instructions. the contents of st remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the br, brl, cal, or call instruction is read, regardless of whether the instruction is executed or skipped. the contents of st are pushed onto the stack during an interrupt and popped from the stack by the rtni instruction?ut not by the rtn instruction. program counter (pc): 14-bit binary counter that points to the rom address of the instruction being executed. stack pointer (sp): ten-bit pointer that contains the address of the stack area to be used next. the sp is initialized to $3ff by mcu reset. it is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is popped from the stack. the top four bits of the sp are fixed at 1111, so a stack can be used up to 16 levels. the sp can be initialized to $3ff also by resetting the rsp bit with the rem or remd instruction. reset the mcu is reset by inputting a high-level voltage to the reset pin. at power-on or when stop mode is cancelled, reset must be high for at least one t rc to enable the oscillator to stabilize. during operation, reset must be high for at least two instruction cycles. see table 1 for initial values after mcu reset. interrupts the mcu has 10 interrupt sources: four external signals ( int 0 , i nt 1 , int 2 , int 3 ), four timer/counters (timers a, b, c, and d), serial interface, and wakeup. an interrupt request flag (if), interrupt mask (im), and vector address are provided for each interrupt source, and an interrupt enable flag (ie) controls the entire interrupt process. some vector addresses are shared by two different interrupts. they are timer a and int 2 , timer b and int 3 , timer c and serial interface. so the type of request that has occurred must be checked at the beginning of interrupt processing. interrupt control bits and interrupt processing: locations $000 to $003 and $022 to $023 in ram are reserved for the interrupt control bits which can be accessed by ram bit manipulation instructions. the interrupt request flag (if) cannot be set by software. mcu reset initializes the interrupt enable flag (ie) and the if to 0 and the interrupt mask (im) to 1.
HD404459 series 14 refer to figure 8 for the block diagram of the interrupt control circuit, table 2 for interrupt priorities and vector addresses, and table 3 for interrupt processing conditions for the 10 interrupt sources. an interrupt request occurs when the if is set to 1 and the im is set to 0. if the ie is 1 at that point, the interrupt is processed. a priority programmable logic array (pla) generates the vector address assigned to that interrupt source. for the interrupt processing sequence, see figure 9, and figure 10 for an interrupt processing flowchart. after an interrupt is acknowledged, the previous instruction is completed in the first cycle. the ie is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. program the jmpl instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the if by a software instruction within the interrupt program.
HD404459 series 15 table 1 initial values after mcu reset item abbr. initial value contents program counter (pc) $0000 indicates program execution point from start address of rom area status flag (st) 1 enables conditional branching stack pointer (sp) $3ff stack level 0 interrupt flags/mask interrupt enable flag (ie) 0 inhibits all interrupts interrupt request flag (if) 0 indicates there is no interrupt request interrupt mask (im) 1 prevents (masks) interrupt requests i/o port data register (pdr) all bits 1 enables output at level 1 data control register (dcd0, dcd1) all bits 0 turns output buffer off (to high impedance) (dcd2) - - 00 (dcr0 dcr8) all bits 0 (dcr9) - 000 port mode register a (pmra) - - 00 refer to description of port mode register a port mode register b (pmrb) 0000 refer to description of port mode register b port mode register c bits 2, 1, 0 (pmrc2, pmrc1, pmrc0) - 000 refer to description of port mode register c detection edge select register 1 (esr1) 0000 disables edge detection detection edge select register 2 (esr2) 00 - - disables edge detection timers/ counters, serial interface timer mode register a (tma) 0000 refer to description of timer mode register a timer mode register b1 (tmb1) 0000 refer to description of timer mode register b1 timer mode register b2 (tmb2) - - 00 refer to description of timer mode register b2 timer mode register c1 (tmc1) 0000 refer to description of timer mode register c1 timer mode register c2 (tmc2) - 000 refer to description of timer mode register c2 timer mode register d1 (tmd1) 0000 refer to description of timer mode register d1 timer mode register d2 (tmd2) 0000 refer to description of timer mode register d2 serial mode register a (smra) 0000 refer to description of serial mode register a serial mode register b (smrb) - - 00 refer to description of serial mode register b
HD404459 series 16 item abbr. initial value contents timers/ counters, serial interface prescaler s (pss) $000 prescaler w (psw) $00 timer counter a (tca) $00 timer counter b (tcb) $00 timer counter c (tcc) $00 timer counter d (tcd) $00 timer write register b (twbu, twbl) $x0 timer write register c (twcu, twcl) $x0 timer write register d (twdu, twdl) $x0 octal counter 000 i/o wakeup set register (wsr) 0000 voltage comparator comparator enable register (cer) 0000 comparator control register (ccr) 0000 bit register low speed on flag (lson) 0 refer to description of operating modes watchdog timer on flag (wdon) 0 refer to description of timer c comparator start flag (cmsf) 0 refer to description of voltage comparator direct transfer on flag (dton) 0 refer to description of operating modes input capture status flag (icsf) 0 refer to description of timer d input capture error flag (icef) 0 refer to description of timer d others miscellaneous register (mis) 0000 refer to description of operating modes, and oscillator circuit system clock select register 1 bits 2, 1 (ssr12 ssr11) 00 refer to description of operating modes, and oscillator circuit system clock select register 2 (ssr2) - - 00 switches osc division ratio notes: 1. the statuses of other registers and flags after mcu reset are shown in the following table. 2. x indicates invalid value. - indicates that the bit does not exist.
HD404459 series 17 item abbr. status after cancellation of stop mode by stopc input status after cancellation of stop mode by mcu reset status after all other types of reset carry flag (ca) pre-stop-mode values are not guaranteed; values must be initialized by program pre-mcu-reset values are not guaranteed; values must be initialized by program accumulator (a) b register (b) w register (w) x/spx register (x/spx) y/spy register (y/spy) serial data register (srl, sru) ram pre-stop-mode values are retained ram enable flag (rame) 1 0 0 port mode register c bit 2 (pmrc) pre-stop-mode values are retained 00 system clock select register1 bit 3 (ssr13) table 2 vector addresses and interrupt priorities reset/interrupt priority vector address reset, stopc * $0000 int 0 1 $0002 int 1 2 $0004 timer d 3 $0006 timer a, int 2 4 $0008 timer b, int 3 5 $000a timer c, serial 6 $000c wakeup 7 $000e note: * the stopc interrupt request is valid only in stop mode.
HD404459 series 18 $000,2 if0 $000,3 im0 int 0 interrupt $001,0 if1 $001,1 im1 int 1 interrupt $001,2 iftd $001,3 imtd timer d interrupt $002,0 ifta $002,1 imta timer a interrupt $002,2 iftb $002,3 imtb timer b interrupt $003,0 iftc $003,1 imtc timer c interrupt $003,2 ifwu $003,3 imwu wakeup interrupt $022,0 $022,1 im2 int 2 interrupt $022,2 $022,3 im3 int 3 interrupt $023,0 ifs $023,1 ims serial interrupt $000,0 ie if2 if3 priority control pla vector address sequence control ? push pc/ca/st ? reset ie ? jump to vector address figure 8 interrupt control circuit
HD404459 series 19 table 3 interrupt processing and activation conditions interrupt source interrupt control bit int 0 int 1 timer d timer a or int 2 timer b or int 3 timer c or serial wakeup ie 11 11 11 1 if0 ? im0 10 00 00 0 if1 ? im1 * 100000 iftd ? imtd ** 10 00 0 ifta ? imta + if2 ? im2 ** * 1000 iftb ? imtb + if3 ? im3 ** ** 10 0 iftc ? imtc + ifs ? ims ** ** * 10 ifwu ? imwu ** ** ** 1 note: bits marked by * can be either 0 or 1. their values have no effect on operation. instruction cycles 123456 instruction execution * ie reset interrupt acceptance execution of jmpl instruction at vector address execution of instruction at start address of interrupt routine vector address generation note: * the stack is accessed and the ie reset after the instruction is executed, even if it is a two-cycle instruction. stacking figure 9 interrupt processing sequence
HD404459 series 20 power on reset = 1? reset mcu interrupt request? execute instruction pc ? (pc) + 1 pc ? $0002 pc ? $0004 pc ? $0006 pc ? $0008 pc ? $000a pc ? $000e ie = 1? interrupt accept ie 0 stack (pc) stack (ca) stack (st) ? int 0 interrupt? int 1 interrupt? timer d interrupt? timer-a/int 2 interrupt? no yes no yes no yes yes yes yes yes yes no no no no ? ? ? (wakeup interrupt) pc ? $000c timer-c/serial interrupt? yes no no timer-b/int 3 interrupt? figure 10 interrupt processing flowchart
HD404459 series 21 interrupt enable flag (ie: $000, bit 0): controls the entire interrupt process. it is reset by the interrupt processing and set by the rtni instruction. refer to table 4. table 4 interrupt enable flag (ie: $000, bit 0) ie interrupt enabled/disabled 0 disabled 1 enabled external interrupts ( int 0 , int 1 , int 2 , int 3 , wu 0 wu 7 ): five external interrupt signals. external interrupt request flags (if0, if1, if2, if3, ifwu: $000, $001, $003, $022): if0, if1, and ifwu are set at the falling edge of input signals, and if2 and if3 are set at the rising or falling edge or both rising and falling edges of input signals (table 5). int 2 and int 3 interrupt edges are selected by the detection edge select register (esr1: $026) (figure 11). table 5 external interrupt request flags (if0?f3, ifwu: $000, $001, $003, $022) if0?f3, ifwu interrupt request 0no 1 yes bit initial value read/write bit name 3 0 w esr13 2 0 w esr12 0 0 w esr10 1 0 w esr11 detection edge selection register 1 (esr1: $026) esr11 0 1 esr10 0 1 0 1 int 2 detection edge no detection falling-edge detection rising-edge detection double-edge detection * esr13 0 1 esr12 0 1 0 1 int 3 detection edge no detection falling-edge detection rising-edge detection double-edge detection * note: * both falling and rising edges are detected. figure 11 detection edge selection register 1 (esr1)
HD404459 series 22 external interrupt masks (im0, im1, im2, im3, imwu: $000, $001, $003, $022): prevent (mask) interrupt requests caused by the corresponding external interrupt request flags (table 6). table 6 external interrupt masks (im0?m3, imwu: $000, $001, $003, $022) im0?m3, imwu interrupt request 0 enabled 1 disabled (masked) timer a interrupt request flag (ifta: $002, bit 0): set by overflow output from timer a (table 7). table 7 timer a interrupt request flag (ifta: $002, bit 0) ifta interrupt request 0no 1 yes timer a interrupt mask (imta: $002, bit 1): prevents (masks) an interrupt request caused by the timer a interrupt request flag (table 8). table 8 timer a interrupt mask (imta: $002, bit 1) imta interrupt request 0 enabled 1 disabled (masked) timer b interrupt request flag (iftb: $002, bit 2): set by overflow output from timer b (table 9). table 9 timer b interrupt request flag (iftb: $002, bit 2) iftb interrupt request 0no 1 yes timer b interrupt mask (imtb: $002, bit 3): prevents (masks) an interrupt request caused by the timer b interrupt request flag (table 10). table 10 timer b interrupt mask (imtb: $002, bit 3) imtb interrupt request 0 enabled 1 disabled (masked)
HD404459 series 23 timer c interrupt request flag (iftc: $003, bit 0): set by overflow output from timer c (table 11). table 11 timer c interrupt request flag (iftc: $003, bit 0) iftc interrupt request 0no 1 yes timer c interrupt mask (imtc: $003, bit 1): prevents (masks) an interrupt request caused by the timer c interrupt request flag (table 12). table 12 timer c interrupt mask (imtc: $003, bit 1) imtc interrupt request 0 enabled 1 disabled (masked) timer d interrupt request flag (iftd: $001, bit 2): set by overflow output from timer d, or by the rising or falling edge of signals input to evnd when the input capture function is used (table 13). table 13 timer d interrupt request flag (iftd: $001, bit 2) iftd interrupt request 0no 1 yes timer d interrupt mask (imtd: $001, bit 3): prevents (masks) an interrupt request caused by the timer d interrupt request flag (table 14). table 14 timer d interrupt mask (imtd: $001, bit 3) imtd interrupt request 0 enabled 1 disabled (masked)
HD404459 series 24 serial interrupt request flags (ifs: $023, bit 0): set when data transfer is completed or when data transfer is suspended (table 15). table 15 serial interrupt request flag (ifs: $023, bit 0) ifs interrupt request 0no 1 yes serial interrupt mask (ims: $023, bit 1): prevents (masks) an interrupt request caused by the serial interrupt request flag (table 16). table 16 serial interrupt mask (ims: $023, bit 1) ims interrupt request 0 enabled 1 disabled (masked) wakeup interrupt request flag (ifwu: $003, bit 2): set by the falling edge of signals input to wakeup (table 17). table 17 wakeup interrupt request flag (ifwu: $003, bit 2) ifwu interrupt request 0no 1 yes wakeup interrupt mask (imwu: $003, bit 3): prevents (masks) an interrupt request caused by the wakeup interrupt request flag (table 18). table 18 wakeup interrupt mask (imwu: $003, bit 3) imwu interrupt request 0 enabled 1 disabled (masked)
HD404459 series 25 wakeup function: detects the falling edge of wakeup input signals and sets the wakeup interrupt request flag (ifwu: $003, bit 2). refer to figure 12 for a block diagram showing the wakeup interrupt. the wakeup select register (wsr: $018) can select from one to eight wakeup inputs ( wu 0 wu 7 ) (figure 13). the wakeup function can operate in any mode other than stop mode. when the wakeup interrupt is received, the cpu generates an independent vector address ($000e). note: the wakeup select register (wsr: $018) controls whether the wakeup input is to be valid or invalid, but it can not switch the pin inputs between the r ports and wakeup. when using the pins only as r ports, nullify wakeup input or set the wakeup interrupt mask (imwu: $003, bit 3). r5 0 / wu 0 r5 1 / wu 1 r5 2 / wu 2 r5 3 / wu 3 r6 0 / wu 4 r6 1 / wu 5 r6 2 / wu 6 r6 3 / wu 7 internal bus falling-edge detection wakeup interrupt request flag wsr (4 bits) wakeup selection register 4 4 figure 12 wakeup interrupt
HD404459 series 26 bit initial value read/write bit name 3 0 w wsr3 2 0 w wsr2 0 0 w wsr0 1 0 w wsr1 wsr0 0 1 wu 0 to wu 3 control invalid valid wsr1 0 1 wu 4 to wu 5 control invalid valid wsr2 0 1 wu 6 control invalid valid wsr3 0 1 wu 7 control invalid valid figure 13 wakeup select register (wsr)
HD404459 series 27 operating modes the mcu has five operating modes (table 19). refer to tables 20 and 21 for the operations in each mode, and figure 14 for the transitions between operating modes. active mode: all mcu functions operate according to the clock generated by the system oscillators osc 1 and osc 2 . table 19 operating modes and clock status mode name active standby stop watch subactive * 2 activation method reset cancellation, interrupt request, stopc cancellation in stop mode, stop/sby instruction in subactive mode (when direct transfer is selected) sby instruction stop instruction when tma3 = 0 stop instruction when tma3 = 1 int 0 , timer a or wakeup interrupt request from watch mode status system oscillator op op stopped stopped stopped subsystem oscillator op op op * 1 op op cancellation method reset input, stop/sby instruction reset input, interrupt request reset input, stopc input in stop mode reset input, int 0 , timer a or wakeup interrupt request reset input, stop/sby instruction note: op implies in operation 1. operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (ssr1 : $029). 2. subactive mode is an optional function; specify it on the function option list.
HD404459 series 28 table 20 operations in low-power dissipation modes function stop mode watch mode standby mode subactive mode * 2 cpu reset retained retained op ram retained retained retained op timer a reset op op op timer b reset stopped op op timer c reset stopped op op timer d reset stopped op op sci reset stopped * 3 op op comparator reset stopped op stopped i/o reset * 1 retained retained op note: op implies in operation 1. output pins are at high impedance. 2. subactive mode is an optional function to be specified on the function option list. 3. transmission/reception is activated if a clock is input in external clock mode. however, all interrupts stop. table 21 i/o status in low-power dissipation modes output input standby mode, watch mode stop mode active mode, subactive mode d 0 ? 9 retained high impedance input enabled d 10 ? 11 input enabled r0?8 r9 0 , r9 1 , r9 2 retained or output of peripheral functions high impedance input enabled r9 3 , ra input enabled
HD404459 series 29 reset by reset input or by watchdog timer f osc : f x : cpu : clk : per : oscillate oscillate stop f cyc f cyc f osc : f x : cpu : clk : per : oscillate oscillate stop f w f cyc f osc : f x : cpu : clk : per : oscillate oscillate f cyc f cyc f cyc f osc : f x : cpu : clk : per : oscillate oscillate f cyc f w f cyc f osc : f x : cpu : clk : per : stop oscillate f sub f w f sub f osc : f x : cpu : clk : per : stop stop stop stop stop f osc : f x : cpu : clk : per : stop oscillate stop f w stop f osc : f x : cpu : clk : per : stop oscillate stop f w stop standby mode stop mode (tma3 = 0, ssr13 = 1) watch mode subactive mode (tma3 = 1) (tma3 = 1, lson = 0) (tma3 = 1, lson = 1) sby interrupt sby interrupt stop * 4 * 2 * 3 1. interrupt source 2. stop/sby (dton = 1, lson = 0) 3. stop/sby (dton = 0, lson = 0) 4. stop/sby (dton = don? care, lson = 1) f osc : f x : f cyc : f sub : f w : lson: dton: main oscillation frequency suboscillation frequency for time-base f osc /4, f osc /8, f osc /16, f osc /32 (software selectable) f x /8 or f x /4 (software selectable) f x /8 system clock clock for time-base clock for other peripheral functions low speed on flag direct transfer on flag active mode notes: cpu : clk : per : f osc : f x : cpu : clk : per : stop oscillate stop stop stop (tma3 = 0, ssr13 = 0) reset1 reset2 rame = 0 rame = 1 * 1 (tma3 = 0) stopc stop int 0 , wu 0 to wu 7 , timer a int 0 , wu 0 to wu 7 , timer a * 1 stopc stop stop figure 14 mcu status transitions
HD404459 series 30 standby mode: in standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. therefore, the cpu operation stops, but all ram and register contents are retained, and the d or r port status, when set to output, is maintained. peripheral functions such as interrupts, timers, and serial interface continue to operate. the power dissipation in this mode is lower than in active mode since the cpu halts. the mcu enters standby mode when the sby instruction is executed in active mode. standby mode is terminated by reset input or an interrupt request. if it is terminated by reset, the mcu is reset as well. after an interrupt request, the mcu enters active mode and executes the next instruction after the sby instruction. if the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. see figure 15 for the flowchart of operation in standby mode. standby oscillator: active peripheral clocks: active all other clocks: stop no yes no yes no yes no yes no yes no yes yes (sby only) watch oscillator: stop suboscillator: active peripheral clocks: stop all other clocks: stop restart processor clocks reset mcu execute next instruction accept interrupt restart processor clocks no yes reset = 1? if0 ? im0 = 1? if1 ? im1 = 1? iftd ? imtd = 1? ifta ? imta + if2 ? im2 = 1? iftb ? imtb + if3 ? im3 = 1? no yes no stop oscillator: stop suboscillator: active/stop peripheral clocks: stop all other clocks: stop reset = 1? stopc = 0? rame = 1 rame = 0 yes yes no no (sby only) (sby only) (sby only) execute next instruction if = 1, im = 0, and ie = 1? * note: * the int 2 interrupt is valid only by standby mode cancellation. ifwu ? imwu = 1? iftc ? imtc + ifs ? ims = 1? figure 15 mcu operation flowchart
HD404459 series 31 stop mode: in stop mode, all mcu operations stop and ram data is retained. therefore, the power dissipation in this mode is the least of all modes. the osc 1 and osc 2 oscillator stops. operation of the x1 and x2 oscillator can be selected by setting bit 3 of the system clock select register (ssr1: $029; operating: ssr13 = 0, stop: ssr13 = 1) (figure 24). the mcu enters stop mode if the stop instruction is executed in active mode when bit 3 of timer mode register a (tma: $008) is set to 0 (tma3 = 0) (figure 40). stop mode is terminated by reset input or stopc input (figure 16). reset or stopc must be applied for at least one t rc to stabilize oscillation (refer to the ac characteristics section). when the mcu restarts after stop mode is cancelled, all ram contents before entering stop mode are retained, but the accuracy of the contents of the accumulator, b register, w register, x/spx register, y/spy register, carry flag, and serial data register cannot be guaranteed. stop mode oscillator internal clock stop instruction execution t res 3 t rc (stabilization period) t res reset stopc figure 16 timing of stop mode cancellation watch mode: in watch mode, the clock function (timer a) using the x1 and x2 oscillator operate but other function operations stop. therefore, the power dissipation in this mode is the second least to stop mode, and is also convenient when only clock display is used. in this mode, the osc 1 and osc 2 oscillator stops, but the x1 and x2 oscillator operates. the mcu enters watch mode if the stop instruction is executed in active mode when tma3 = 1, or if the stop or sby instruction is executed in subactive mode. watch mode is terminated by a reset input, timer a interrupt request, int 0 interrupt request, or wakeup interrupt request. for details of reset input, refer to the stop mode section. when terminated by a timer a interrupt request, an int 0 nterrupt request, or wakeup interrupt request, the mcu enters active mode if lson is 0 or subactive mode if lson is 1. after an interrupt request is generated, the time required to enter active mode is t rc for a timer a interrupt, and t x (where t + t rc < t x < 2t + t rc ) for an int 0 interrupt, as shown in figure 17. operation during mode transition is the same as that at standby mode cancellation (figure 15).
HD404459 series 32 active mode watch mode active mode oscillation stabilization period interrupt strobe inte, rupt, trobe int , wu ? wu interrupt request generation (during the transition from watch mode to active mode only) 0 0 7 ttt rc tx t: t : rc interrupt frame length oscillation stabilization period t + < tx < 2t + t rc t rc figure 17 interrupt frame subactive mode: the osc 1 and osc 2 oscillator stops and the mcu operates with a clock generated by the x1 and x2 oscillator. in this mode, functions other than the voltage comparator operate. however, because the operating clock is slow, the power dissipation becomes low, next to watch mode. the cpu instruction execution speed can be selected as 244 m s or 122 m s by setting bit 2 (ssr12) of the system clock select register (ssr1: $029). note that the ssr12 value must be changed in active mode. if the value is changed in subactive mode, the mcu may malfunction. when the stop or sby instruction is executed in subactive mode, the mcu enters either watch or active mode, depending on the statuses of the low speed on flag (lson: $020, bit 0) and the direct transfer on flag (dton: $020, bit 3). subactive mode is an optional function that the user must specify on the function option list. interrupt frame: in watch and subactive modes, clk is applied to timer a and the int 0 and wu 0 wu 7 circuits. prescaler w and timer a operate as the time-base and generate the timing clock for the interrupt frame. three interrupt frame lengths (t) can be selected by setting the miscellaneous register (mis: $00c) (figure 18). in watch and subactive modes, a timer a/ int 0 wakeup interrupt is generated synchronously with the interrupt frame. the interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. the falling edge of the int 0 and wu 0 wu 7 signals is input asynchro- nously with the interrupt frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the falling edge. an overflow and interrupt request in timer a is generated synchronously with the interrupt strobe timing.
HD404459 series 33 bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 miscellaneous register (mis: $00c) mis1 0 mis0 t * 1 0 0.24414 ms t rc * 1 0.12207 ms 0.24414 ms * 2 7.8125 ms 62.5 ms oscillation circuit conditions external clock input ceramic or crystal oscillator 1 1 0 1 15.625 ms 125 ms not used notes: 1. 2. the values of t and t rc are applied when a 32.768-khz crystal oscillator is used. the value is applied only when direct transfer operation is used. buffer control. refer to figure 39. mis3 mis2 figure 18 miscellaneous register (mis) direct transition from subactive mode to active mode: available by controlling the direct transfer on flag (dton: $020, bit 3) and the low speed on flag (lson: $020, bit 0). the procedures are described below: 1. set lson to 0 and dton to 1 in subactive mode. 2. execute the stop or sby instruction. 3. the mcu automatically enters active mode from subactive mode after waiting for the mcu internal processing time and oscillation stabilization time (figure 19). notes: the dton flag ($020, bit 3) can be set only in subactive mode. it is always reset in active mode. the transition time (t d ) from subactive mode to active mode is: t rc < t d < t + t rc
HD404459 series 34 subactive mode interrupt strobe direct transfer completion timing mcu internal processing period oscillation stabilization time active mode t t rc t: t : rc stop/sby instruction execution (set lson = 0, dton = 1) interrupt frame length oscillation stabilization period figure 19 direct transition timing stop mode cancellation by stopc : the mcu enters active mode from stop mode by a stopc input as well as by reset. in either case, the mcu starts instruction execution from the starting address (address 0) of the program. however, the value of the ram enable flag (rame: $021, bit 3) differs between cancellation by stopc and by reset. when stop mode is cancelled by reset, rame = 0; when cancelled by stopc , rame = 1. reset can cancel all modes, but stopc is valid only in stop mode; stopc input is ignored in other modes. therefore, when the program requires to confirm that stop mode has been cancelled by stopc (i.e., when the ram contents before entering stop mode are used after transition to active mode), execute the test instruction on the ram enable flag (rame) at the beginning of the program. mcu operation sequence: see figures 20 to 22 for the mcu operation sequences. it is reset by an asynchronous reset input, regardless of its status. the low-power mode operation sequence is shown in figure 22. with the ie flag cleared and an interrupt flag set together with its interrupt mask cleared, if a stop/sby instruction is executed, the instruction is cancelled (regarded as an nop) and the following instruction is executed. before executing a stop/sby instruction, make sure all interrupt flags are cleared or all interrupts are masked.
HD404459 series 35 power on reset = 1? rame = 0 reset mcu mcu operation cycle no yes figure 20 mcu operating sequence (power on)
HD404459 series 36 mcu operation cycle if = 1? instruction execution sby, stop instruction? pc next location pc vector address low-power mode operation cycle ie 0 stack (pc), (ca), (st) im = 0 and ie = 1? ? ? ? yes no no yes yes no if: im: ie: pc: ca: st: ? interrupt request flag interrupt mask interrupt enable flag program counter carry flag status flag figure 21 mcu operating sequence (mcu operation cycle)
HD404459 series 37 low-power mode operation cycle if = 1 and im = 0? hardware nop execution ? pc next iocation mcu operation cycle standby/watch mode if = 1 and im = 0? hardware nop execution pc next iocation ? instruction execution stop mode no yes no yes note: * for if and im operation, refer to figure 15. stopc = 0? rame = 1 reset mcu no yes * figure 22 mcu operating sequence (low-power mode operation)
HD404459 series 38 notes on use: when the mcu is in watch mode or subactive mode, if the high level period before the falling edge of int 0 and wu 0 wu 7 is shorter than the interrupt frame, int 0 and wu 0 wu 7 will not be detected. also, if the low level period after the falling edge of int 0 and wu 0 wu 7 is shorter than the interrupt frame, int 0 and wu 0 wu 7 will not be detected. edge detection is shown in figure 23. the level of the int 0 and wu 0 wu 7 signals are sampled by a sampling clock. when this sampled value changes from high to low, a falling edge is detected. in figure 24, the level of the int 0 and wu 0 wu 7 signals are sampled by an interrupt frame. in (a) the sampled value is low at point a, and also low at point b. therefore, a falling edge will not be detected. in (b), the sampled value is high at point a, and also high at point b. a falling edge will not be detected in this case either. when the mcu is in watch mode or subactive mode, keep the high level and low level periods of int 0 and wu 0 wu 7 longer than interrupt frame. high low int 0 , wu 0 wu 7 sampling low figure 23 edge detection a: low b: low int 0 , wu 0 wu 7 interrupt frame a: high b: high int 0 , wu 0 wu 7 interrupt frame a. high level period b. low level period figure 24 sampling example
HD404459 series 39 internal oscillator circuit clock generation circuit see figure 25 for a block diagram of the clock generation circuit. a ceramic oscillator or crystal oscillator can be connected to osc 1 and osc 2 , and a 32.768-khz oscillator can be connected to x1 and x2 (table 22). the system oscillator can also be operated by an external clock. bit 1 (ssr11) of system clock select register 1 (ssr1: $029) must be selected according to the frequency of the oscillator connected to osc 1 and osc 2 (figure 26). note: if the system clock select register 1 (ssr1: $029) setting does not match the oscillator frequency, subsystems using the 32.768-khz oscillation will malfunction. osc 2 osc 1 x1 x2 system oscillator sub- system oscillator 1/4, 1/8, 1/16, or 1/32 division circuit * 1 timing generator circuit system clock selection circuit cpu with rom, ram, registers, flags, and i/o peripheral function interrupt time-base interrupt time-base clock selection circuit 1/8 or 1/4 division circuit * 2 timing generator circuit timing generator circuit 1/8 division circuit f w f sub t lson tma3 f cyc t cyc f osc f x t wcyc cpu ? per clk notes: 1. 2. 1/4, 1/8, 1/16, or 1/32 division ratio can be selected by setting bits 0 and 1 of system clock select register 2 (ssr2). 1/8 or 1/4 division ratio can be selected by setting bit 2 of system clock select register 1 (ssr1). subcyc figure 25 clock generation circuit
HD404459 series 40 selection of division ratio division ratio of the system clock: 1/4, 1/8, 1/16, or 1/32 division ratio of the system clock can be selected by setting bits 0 and 1 (ssr20 and ssr21) of system clock select register 2 (ssr2: $02a). the values of ssr20 and ssr21 become valid when entering the watch mode after making the ratio selection. (however, the value of ssr2 becomes valid immediately after the selection.) therefore, when changing the division ratio, the system clock must be stopped. there are two methods for selecting the division ratio of the system clock as follows. division ratio is selected by writing to ssr20 and ssr21 in active mode. the selected values of ssr20 and ssr21 are valid before the mcu enters watch mode. the division ratio of the system clock becomes the written value when the mcu returns to the active mode from the watch mode. division ratio is selected by writing to ssr20 and ssr21 in subactive mode. the division ratio of the system clock becomes the selected value when the mcu returns to active mode after entering watch mode. note: ssr2 is cleared in the reset and stop modes. therefore, 1/4 division ratio of the system clock is selected when the mcu returns from stop mode after reset. division ratio of the subsystem clock: 1/4 or 1/8 division ratio of the subsystem clock can be selected by setting bit 2 (ssr12) of system clock select register 1 (ssr1: $029). the value of ssr12 becomes valid immediately after the ratio selection. when the value of ssr12 is changed, the mcu must be in active mode. if the value of ssr12 is changed in subactive mode, the mcu may malfunction.
HD404459 series 41 ssr11 0 1 system oscillation frequency selection 1.6 to 4.0 mhz 0.4 to 1.0 mhz bit initial value read/write bit name 3 0 w ssr13 * 2 0 w ssr12 0 not used 1 0 w ssr11 system clock select register 1 (ssr1: $029) ssr13 0 1 32-khz oscillation stop oscillation operates in stop mode oscillation stops in stop mode ssr12 0 1 32-khz oscillation division ratio selection f sub = fx/8 f sub = fx/4 note: * ssr13 is reset to 0 only by reset input. when stopc is input in stop mode, ssr13 is not reset but retains its value. ssr13 is not reset in stop mode. figure 26 system clock select register 1 (ssr1: $029) bit initial value read/write bit name 3 not used 2 not used 0 0 w ssr20 1 0 w ssr21 system clock select register 2 (ssr2: $02a) ssr21 0 1 system clock division ratio selection 1/4 1/8 1/16 1/32 ssr20 0 1 0 1 figure 27 system clock select register 2 (ssr2: $02a)
HD404459 series 42 reset x1 x2 gnd osc 2 osc 1 test gnd figure 28 typical layout of crystal and ceramic oscillators
HD404459 series 43 table 22 oscillator circuit examples circuit configuration circuit constants external clock operation external oscillator osc open 1 osc 2 ceramic oscillator (osc 1 , osc 2 ) osc 2 c 1 2 c osc 1 r f ceramic gnd ceramic oscillator: csa4.00mg (murata) r f = 1 m w 20% c 1 = c 2 = 30 pf crystal oscillator (osc 1 , osc 2 ) c 1 2 c crystal gnd l s c r s c 0 f r osc 1 osc 2 osc 2 osc 1 r f = 1 m w 20% c 1 = c 2 = 10?2 pf 20% crystal: equivalent to circuit shown below c 0 : 7 pf max. r s : 100 w max. crystal oscillator (x1, x2) x1 c 1 2 c x2 crystal gnd l s c r s c 0 x1 x2 crystal: 32.768 khz: mx38t (nippon denpa kogyo) c 1 = c 2 = 15 pf 5% r s : 14 k w c 0 : 1.5 pf notes: 1. since the circuit constants change depending on the crystal or ceramic resonator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. wiring among osc 1 , osc 2 , x1, x2, and elements should be as short as possible, and must not cross other wiring (figure 28). 3. if the 32.768-khz crystal oscillator is not used, the x1 pin must be fixed to gnd and x2 must be open.
HD404459 series 44 input/output the mcu has 49 input/output pins (d 0 ? 9 , r0?8, r9 0 ?9 2 ) and 7 input pins (d 10 , d 11 , r9 3 , ra). the features are described as follows. the d 11 , r0, r3?6, r9 3 , and ra pins are multiplexed with peripheral function pins such as those for timers or the serial interface. see table 24. for these pins, the peripheral function setting is done prior to the d or r port setting. therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting. however, pins input to the wakeup function are not switched. only the valid/invalid statuses of wakeup input are controlled. peripheral function output pins are cmos out-put pins. see table 23. only the so pin and r4 3 port can be set to nmos open-drain output by software. in stop mode, the mcu is reset, and therefore peripheral function selection is cancelled. input/output pins are set at high-impedance. each input/output pin has a built-in pull-up mos (figure 29), which can be individually turned on or off by software.
HD404459 series 45 table 23 programmable i/o circuits mis3 (bit 3 of mis) 0 1 dcd, dcr 0 1 0 1 pdr 0101 0101 cmos buffer pmos ?n?n nmos on on pull-up mos ?non note: ?indicates off status. mis3 input control signal v cc pull-up mos dcd, dcr pdr input data v cc hlt pull-up control signal buffer control signal output data figure 29 i/o buffer configuration
HD404459 series 46 table 24 circuit configurations of i/o pins i/o pin type circuit pins input/output pins v cc v cc pull-up control signal buffer control signal output data input data hlt mis3 dcd, dcr pdr input control signal d 0 ? 9 , r0 0 ?0 3 , r1 0 ?1 3 , r2 0 ?2 3 , r3 0 ?3 3 , r4 0 ?4 2 , r5 0 ?5 3 , r6 0 ?6 3 , r7 0 ?7 3 , r8 0 ?8 3 , r9 0 ?9 2 v cc v cc pull-up control signal buffer control signal output data input data hlt mis3 dcr pdr input control signal mis2 r4 3 input pins input data input control signal d 10 , d 11 , r9 3 , ra 0 ?a 3 peripheral function pins input/ output pins v cc v cc pull-up control signal output data input data hlt mis3 sck sck sck output pins v cc v cc pull-up control signal pmos control signal output data hlt mis3 so mis2 so v cc v cc pull-up control signal output data hlt mis3 tob, toc, tod tob, toc, tod
HD404459 series 47 i/o pin type circuit pins peripheral function pins input pins v cc int 0 , etc hlt mis3 pdr si, int 0 , int 1 , int 2 , int 3 , wu 0 wu 7 , evnb , evnd input data stopc stopc notes: 1. in stop mode, the mcu is reset and peripheral function selection is cancelled. the hlt signal becomes low, and input/output pins enter high-impedance state. 2. the hlt signal is 1 in watch and subactive modes. d port (d 0 ? 11 ): consist of 10 input/output pins and 2 input pins addressed by one bit. d 0 ? 9 are input/output pins, and d 10 and d 11 are input-only pins. pins d 0 ? 9 are set by the sed and sedd instructions, and reset by the red and redd instructions. output data is stored in the port data register (pdr) for each pin. all pins d 0 ? 11 are tested by the td and tdd instructions. the on/off statuses of the output buffers are controlled by d-port data control registers (dcd0?cd2: $02c?02e) that are mapped to memory addresses (figure 30). pin d 11 is multiplexed with peripheral function pin stopc . the peripheral function mode of this pin is selected by bit 2 (pmrc2) of port mode register c (pmrc: $025) (figure 35).
HD404459 series 48 r ports (r0?a): 39 input/output pins and 5 input pins addressed in 4-bit units. data is input to these ports by the lar and lbr instructions, and output from them by the lra and lrb instructions. output data is stored in the port data register (pdr) for each pin. the on/off statuses of the output buffers of the r ports are controlled by r-port data control registers (dcr0?cr9: $030?039) that are mapped to memory addresses (figure 30). bit initial value read/write bit name 3 0 w dcd03, 2 0 w dcd02, 0 0 w dcd00, 1 0 w dcd01, dcd0, dcd1 data control register (dcd0 to dcd2: $02c to $02e) (dcr0 to dcr9: $030 to $039) dcd13 dcd12 dcd10 dcd11 bit initial value read/write bit name 3 not used 2 not used 0 0 w dcd20 1 0 w dcd21 dcd2 bit initial value read/write bit name 3 0 w dcr03 2 0 w dcr02 0 0 w dcr00 1 0 w dcr01 dcr0 to dcr8 dcr83 dcr82 dcr80 dcr81 bit initial value read/write bit name 3 not used 2 0 w dcr92 0 0 w dcr90 1 0 w dcr91 dcr9 correspondence between ports and dcd/dcr bits 0 1 dcd0 dcd1 dcd2 dcr0 dcr1 dcr2 dcr3 dcr4 dcr5 dcr6 dcr7 dcr8 dcr9 off (high-impedance) on all bits cmos buffer on/off selection register name d 3 d 7 r0 3 r1 3 r2 3 r3 3 r4 3 r5 3 r6 3 r7 3 r8 3 bit 3 d 2 d 6 r0 2 r1 2 r2 2 r3 2 r4 2 r5 2 r6 2 r7 2 r8 2 r9 2 bit 2 d 1 d 5 d 9 r0 1 r1 1 r2 1 r3 1 r4 1 r5 1 r6 1 r7 1 r8 1 r9 1 bit 1 d 0 d 4 d 8 r0 0 r1 0 r2 0 r3 0 r4 0 r5 0 r6 0 r7 0 r8 0 r9 0 bit 0 figure 30 data control registers (dcd, dcr)
HD404459 series 49 pins r0 0 ?0 3 are multiplexed with peripheral pins int 0 ?nt 3 , respectively. the peripheral function modes of these pins are selected by bits 0? (pmrb0?mrb3) of port mode register b (pmrb: $024) (figure 31). /int bit initial value read/write bit name 3 0 w pmrb3 2 0 w pmrb2 0 0 w pmrb0 1 0 w pmrb1 pmrb0 0 1 r0 0 / int 0 mode selection r0 0 int 0 port mode register b (pmrb: $024) pmrb1 0 1 mode selection r0 1 / int 1 mode selection 2 r0 1 int 1 pmrb2 0 1 mode selection r0 2 /int 3 r0 2 int 2 pmrb3 0 1 r0 3 r0 3 int 3 figure 31 port mode register b (pmrb)
HD404459 series 50 pins r3 0 ?3 2 are multiplexed with peripheral pins tob, toc, and tod, respectively. the peripheral function modes of these pins are selected by bits 0 and 1 (tmb20, tmb21) of timer mode register b2 (tmb2: $013), bits 0? (tmc20?mc22) of timer mode register c2 (tmc2: $014), and bits 0? (tmd20?md23) of timer mode register d2 (tmd2: $015) (figures 32, 33, and 34). bit initial value read/write bit name 3 not used 2 not used 0 0 r/w tmb20 1 0 r/w tmb21 timer mode register b2 (tmb2: $013) tmb21 0 1 tmb20 0 1 0 1 r3 0 /tob mode selection r3 0 tob tob tob r3 0 port toggle output 0 output 1 output figure 32 timer mode register b2 (tmb2) bit initial value read/write bit name 3 not used 2 0 r/w tmc22 0 0 r/w tmc20 1 0 r/w tmc21 timer mode register c2 (tmc2: $014) tmc20 0 1 0 1 0 1 0 1 r3 toc toc toc toc toc toc toc 1 r3 1 /toc mode selection tmc21 0 1 0 1 tmc22 0 1 r3 1 port toggle output 0 output 1 output not used not used not used pwm output figure 33 timer mode register c2 (tmc2)
HD404459 series 51 bit initial value read/write bit name 3 0 r/w tmd23 2 0 r/w tmd22 0 0 r/w tmd20 1 0 r/w tmd21 timer mode register d2 (tmd2: $015) tmd20 0 1 0 1 0 1 0 1 don't care r3 tod tod tod tod tod tod tod r3 2 2 r3 2 /tod mode selection tmd21 0 1 0 1 don't care tmd22 0 1 don't care r3 2 port toggle output 0 output 1 output not used not used not used pwm output input capture (r3 2 port) tmd23 0 1 figure 34 timer mode register d2 (tmd2)
HD404459 series 52 pins r3 3 and r4 0 are multiplexed with peripheral pins evnb and evnd, respectively. the peripheral function modes of these pins are selected by bits 0 and 1 (pmrc0, pmrc1) of port mode register c (pmrc: $025) (figure 35). bit initial value read/write bit name 3 not used 2 0 w pmrc2 * 0 0 w pmrc0 1 0 w pmrc1 port mode register c (pmrc: $025) pmrc0 0 1 r3 3 pmrc1 0 1 r4 0 /evnd mode selection r4 0 evnd r3 3 / evnb mode selection evnb pmrc2 0 1 d 11 stopc d 11 / stopc mode selection note: * pmrc2 is reset to 0 only by reset input. when stopc is input in stop mode, pmrc2 is not reset but retains its value. figure 35 port mode register c (pmrc)
HD404459 series 53 pins r4 1 ?4 3 are multiplexed with peripheral pins sck , si, and so, respectively. the peripheral function modes of these pins are selected by bit 3 (smra3) of serial mode register a (smra: $005), and bits 0 and 1 (pmra0, pmra1) port mode register a (pmra: $004) (figures 36 and 37). pmra0 0 1 r4 3 /so mode selection r4 3 so bit initial value read/write bit name 3 not used 2 not used 0 0 w pmra0 1 0 w pmra1 port mode register a (pmra: $004) pmra1 0 1 r4 2 /si mode selection r4 2 si figure 36 port mode register a (pmra) bit initial value read/write bit name 3 0 w smra3 2 0 w smra2 0 0 w smra0 1 0 w smra1 serial mode register a (smra: $005) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 output output output output output output output input prescaler prescaler prescaler prescaler prescaler prescaler system clock external clock ? 2048 ? 512 ? 128 ? 32 ? 8 ? 2 prescaler division ratio smra2 smra0 smra1 clock source smra3 0 1 r4 1 / sck mode selection sck r4 1 port sck figure 37 serial mode register a (smra)
HD404459 series 54 ports r5 and r6 are multiplexed with pins wu 0 wu 7 . the wakeup modes of these pins can be selected by the wakeup select register (wsr: $018). even if wakeup input is valid, the r port functions normally (figure 38). bit initial value read/write bit name 3 0 w wsr3 2 0 w wsr2 0 0 w wsr0 1 0 w wsr1 wsr0 0 1 wu 0 to wu 3 control invalid valid wakeup select register (wsr: $018) wsr1 0 1 wu 4 to wu 5 control invalid valid wsr2 0 1 wu 6 control invalid valid wsr3 0 1 wu 7 control invalid valid figure 38 wakeup select register (wsr)
HD404459 series 55 pull-up mos transistor control: a program-controlled pull-up mos transistor is provided for each input/output pin other than input-only pins d 10 , d 11 , r9 3 , and ra 0 ?a 3 . the on/off status of all these transistors is controlled by bit 3 (mis3) of the miscellaneous register (mis: $00c), and the on/off status of an individual transistor can also be controlled by the port data register (pdr) of the corresponding pin enabling on/off control of that pin alone (table 23 and figure 39). the on/off status of each transistor and the peripheral function mode of each pin can be set independently. bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 mis2 cmos buffer on/off selection for pin r4 3 /so miscellaneous register (mis: $00c) 0 1 on off refer to figure 18 in the operation modes section. t rc selection. mis3 0 1 pull-up mos on/off selection off on mis1 mis0 figure 39 miscellaneous register (mis) how to deal with unused i/o pins: i/o pins that are not needed by the user system (those that remain floating) must be connected to v cc to prevent lsi malfunctions due to noise. these pins must either be pulled up to v cc by their pull-up mos transistors or by resistors of about 100 k w .
HD404459 series 56 prescalers the mcu has two prescalers, s and w. see table 25 and figure 40. both the timers a? input clocks except external events and the serial transmit clock except the external clock are selected from the prescaler outputs, depending on corresponding mode registers. 32-khz crystal oscillator system clock prescaler w prescaler s timer a timer b timer c timer d serial clock selector f x /8 f x /4 or f x /8 figure 40 prescaler output supply prescaler operation prescaler s: 11-bit counter that inputs a system clock signal. after being reset to $000 by mcu reset, prescaler s divides the system clock. prescaler s keeps counting, except in watch and stop modes and at mcu reset. prescaler w: five-bit counter that inputs the x1 input clock signal (32-khz crystal oscillation) divided. after being reset to $00 by mcu reset, prescaler w divides the input clock. prescaler w can be reset by software. table 25 prescaler operating conditions prescaler input clock reset conditions stop conditions prescaler s system clock (in active and standby mode), subsystem clock (in subactive mode) mcu reset mcu reset, stop mode, watch mode prescaler w 32-khz crystal oscillation mcu reset, software mcu reset, stop mode
HD404459 series 57 timers the mcu has four timer/counters (a to d). ? timer a: free-running timer ? timer b: multifunction timer ? timer c: multifunction timer ? timer d: multifunction timer timer a is an 8-bit free-running timer. timers b? are 8-bit multifunction timers (table 26). the operating modes are selected by software. table 26 timer functions functions timer a timer b timer c timer d clock source prescaler s available available available available prescaler w available external event available available timer functions free-running available available available available time-base available event counter available available reload available available available watchdog available input capture available timer outputs toggle available available available 0 output available available available 1 output available available available pwm available available note: ?means not available.
HD404459 series 58 timer a timer a functions: timer a (figure 41) has the following functions. free-running timer clock time-base 1/4 1/2 32.768-khz oscillator system clock prescaler w (psw) selector selector prescaler s (pss) selector internal data bus timer a interrupt request flag (ifta) clock overflow timer counter a (tca) timer mode register a (tma) 3 2 f 1/2 t wcyc f t wcyc per 2 4 8 32 128 512 1024 2048 ? ? ? ? ? ? ? ? 2 8 16 32 ? ? ? ? w w figure 41 block diagram of timer a timer a operations: free-running timer operation: the input clock for timer a is selected by timer mode register a (tma: $008). timer a is reset to $00 by mcu reset and incremented at each input clock. if an input clock is applied to timer a after it has reached $ff, an overflow is generated, and timer a is reset to $00. the overflow sets the timer a interrupt request flag (ifta: $002, bit 0). timer a continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. clock time-base operation: timer a is used as a clock time-base by setting bit 3 (tma3) of timer mode register a (tma: $008) to 1. the prescaler w output is applied to timer a, and timer a generates interrupts at the correct timing based on the 32.768-khz crystal oscillation. in this case, prescaler w and timer a can be reset to $00 by software.
HD404459 series 59 registers for timer a operation: timer a operating modes are set by the following registers. timer mode register a (tma: $008): four-bit write-only register that selects timer a? operating mode and input clock source (figure 42). bit initial value read/write bit name 3 0 w tma3 2 0 w tma2 0 0 w tma0 1 0 w tma1 timer mode register a (tma: $008) 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 pss pss pss pss pss pss pss pss psw psw psw psw psw operating mode timer a mode tma3 tma1 tma2 tma0 source prescaler 2048t cyc 1024t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc input clock frequency 0 1 1 32t wcyc 16t wcyc 8t wcyc 2t wcyc 1/2t wcyc time-base mode 0 0 1 1 0 1 1 not used psw and tca reset don't care note: 1. 2. 3. t wcyc = 244.14 m s (when a 32.768-khz crystal oscillator is used) timer counter overflow output period (seconds) = input clock period (seconds) 256. the division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. figure 42 timer mode register a (tma)
HD404459 series 60 timer b timer b functions: timer b (figure 43) has the following functions. free-running/reload timer external event counter timer output operation (toggle, 0, and 1 outputs) system clock evnb tob timer output control selector prescaler s (pss) clock timer read register bu (trbu) timer read register bl (trbl) timer/event counter b (tcb) timer write register bu (twbu) timer write register bl (twbl) timer mode register b1 (tmb1) timer mode register b2 (tmb2) timer b interrupt request flag (iftb) per 3 2 internal data bus 2 4 8 32 128 512 2048 ? ? ? ? ? ? ? free-running/ reload control overflow timer output control logic figure 43 block diagram of timer b
HD404459 series 61 timer b operations: free-running/reload timer operation: the free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register b1 (tmb1: $009). timer b is initialized to the value set in timer write register b (twbl: $00a, twbu: $00b) by software and incremented by one at each clock input. if an input clock is applied to timer b after it has reached $ff, an overflow is generated. in this case, if the reload timer function is enabled, timer b is initialized to its initial value set in timer write register b; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. the overflow sets the timer b interrupt request flag (iftb: $002, bit 2). iftb can be reset by software or mcu reset. refer to figure 3 and table 1 for details. external event counter operation: timer b is used as an external event counter by selecting external event input as the input clock source. in this case, pin r3 3 / evnb must be set to evnb by port mode register c (pmrc: $025). timer b is incremented by one at each falling edge of signals input to pin evnb . the other operations are basically the same as the free-running/ reload timer operation. timer output operation: the following three output modes can be selected for timer b by setting timer mode register b2 (tmb2: $013). ? toggle ? 0 output ? 1 output by selecting the timer output mode, pin r3 0 /tob is set to tob. the output from tob is reset low by mcu reset. ? toggle output: when toggle output mode is selected, the output level is inverted if a clock is input after timer b has reached $ff. by using this function and reload timer function, clock signals can be output at a required frequency for a buzzer. refer to figure 44 for the output waveform. ? 0 output: when 0 output mode is selected, the output level is pulled low if a clock is input after timer b has reached $ff. note that this function must be used only when the output level is high. ? 1 output: when 1 output mode is selected, the output level is set high if a clock is input after timer b has reached $ff. note that this function must be used only when the output level is low.
HD404459 series 62 t (n + 1) t 256 t t (256 ?n) tmc13 = 0 the waveform is always fixed low when n = $ff. t: n: tmc13 = 1 input clock period to counter (figures 45, 53, and 60) the value of the timer write register (figures 55, 56, 62, and 63) note: tmd13 = 0 tmd13 = 1 256 clock cycles 256 clock cycles free-running timer toggle output waveform (timers b, c, and d) pwm output waveform (timers c and d) (256 ?n) clock cycles (256 ?n) clock cycles reload timer figure 44 timer output waveform registers for timer b operation: by using the following registers, timer b operation modes are selected and the timer b count is read and written. ? timer mode register b1 (tmb1: $009) ? timer mode register b2 (tmb2: $013) ? timer write register b (twbl: $00a, twbu: $00b) ? timer read register b (trbl: $00a, trbu: $00b) ? port mode register c (pmrc: $025) timer mode register b1 (tmb1: $009): four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio (figure 45). it is reset to $0 by mcu reset.
HD404459 series 63 the mode change of this register is valid from the second instruction execution cycle after the execution of the previous timer mode register b1 write instruction. setting timer b? initialization by writing to timer write register b (twbl: $00a, twbu: $00b) must be done after a mode change becomes valid. bit initial value read/write bit name 3 0 w tmb13 2 0 w tmb12 0 0 w tmb10 1 0 w tmb11 timer mode register b1 (tmb1: $009) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmb12 tmb10 tmb11 input clock period and input clock source r3 3 / evnb (external event input) tmb13 0 1 free-running/reload timer selection free-running timer reload timer figure 45 timer mode register b1 (tmb1)
HD404459 series 64 timer mode register b2 (tmb2: $013): two-bit read/write register that selects the timer b output mode (figure 46). it is reset to $0 by mcu reset. bit initial value read/write bit name 3 not used 2 not used 0 0 r/w tmb20 1 0 r/w tmb21 timer mode register b2 (tmb2: $013) tmb21 0 1 tmb20 0 1 0 1 r3 0 /tob mode selection r3 0 tob tob tob r3 0 port toggle output 0 output 1 output figure 46 timer mode register b2 (tmb2) timer write register b (twbl: $00a, twbu: $00b): write-only register consisting of a lower digit (twbl) and an upper digit (twbu) (figures 47 and 48). the lower digit is reset to $0 by mcu reset, but the upper digit value is undefined. timer b is initialized by writing to timer write register b (twbl: $00a, twbu: $00b). in this case, the lower digit (twbl) must be written to first, but writing only to the lower digit does not change the timer b value. timer b is initialized to the value in timer write register b at the same time the upper digit (twbu) is written to. when timer write register b is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer b. bit initial value read/write bit name 3 0 w twbl3 2 0 w twbl2 0 0 w twbl0 1 0 w twbl1 timer write register b (lower digit) (twbl: $00a) figure 47 timer write register b lower digit (twbl)
HD404459 series 65 bit initial value read/write bit name 3 undefined w twbu3 2 undefined w twbu2 0 undefined w twbu0 1 undefined w twbu1 timer write register b (upper digit) (twbu: $00b) figure 48 timer write register b upper digit (twbu) timer read register b (trbl: $00a, trbu: $00b): read-only register consisting of a lower digit (trbl) and an upper digit (trbu) that holds the count of the timer b upper digit. the upper digit (trbu) must be read first, which will result in the count of the timer b upper digit to be obtained and the count of the timer b lower digit to be latched to the lower digit (trbl). then by reading trbl, the count of timer b can be obtained when trbu is read. bit initial value read/write bit name 3 undefined r trbl3 2 undefined r trbl2 0 undefined r trbl0 1 undefined r trbl1 timer read register b (lower digit) (trbl: $00a) figure 49 timer read register b lower digit (trbl) bit initial value read/write bit name 3 undefined r trbu3 2 undefined r trbu2 0 undefined r trbu0 1 undefined r trbu1 timer read register b (upper digit) (trbu: $00b) figure 50 timer read register b upper digit (trbu)
HD404459 series 66 port mode register c (pmrc: $025): write-only register that selects the r3 3 / evnb pin function (figure 51). it is reset to $0 by mcu reset. bit initial value read/write bit name 3 not used 2 0 w pmrc2 0 0 w pmrc0 1 0 w pmrc1 pmrc1 0 1 r4 0 /evnd mode selection r4 0 evnd port mode register c (pmrc: $025) pmrc0 0 1 r3 3 / evnb mode selection r3 3 evnb pmrc2 0 1 d 11 / stopc mode selection d 11 stopc figure 51 port mode register c (pmrc)
HD404459 series 67 timer c timer c functions: timer c (figure 52) has the following functions. ? free-running/reload timer ? watchdog timer ? timer output operation (toggle, 0, 1, and pwm outputs) watchdog on flag (wdon) system reset signal timer c interrupt request flag (iftc) timer output control logic timer read register cu (trcu) timer output control timer read register cl (trcl) clock timer counter c (tcc) selector system clock prescaler s (pss) overflow internal data bus timer write register cu (twcu) timer write register cl (twcl) timer mode register c1 (tmc1) timer mode register c2 (tmc2) free-running /reload control watchdog timer control logic toc per 2 4 8 32 128 512 1024 2048 3 3 figure 52 block diagram of timer c
HD404459 series 68 timer c operations: free-running/reload timer operation: the free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register c1 (tmc1: $00d). timer c is initialized to the value set in timer write register c (twcl: $00e, twcu: $00f) by software and incremented by one at each clock input. if an input clock is applied to timer c after it has reached $ff, an overflow is generated. in this case, if the reload timer function is enabled, timer c is initialized to its initial value set in timer write register c; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. the overflow sets the timer c interrupt request flag (iftc: $003, bit 0). iftc can be reset by software or mcu reset. refer to figure 3 and table 1 for details. watchdog timer operation: timer c is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (wdon: $020, bit 1) to 1. if a program routine runs out of control and an overflow is generated, the mcu is reset. program run can be controlled by initializing timer c by software before it reaches $ff. timer output operation: the following four output modes can be selected for timer c by setting timer mode register c2 (tmc2: $014). ? toggle ? 0 output ? 1 output ? pwm output by selecting the timer output mode, pin r3 1 /toc is set to toc. the output from toc is reset low by mcu reset. ? toggle output: the operation is basically the same as that of timer-b? toggle output. ? 0 output: the operation is basically the same as that of timer-b? 0 output. ? 1 output: the operation is basically the same as that of timer-b? 1 output. ? pwm output (figure 44): when pwm output mode is selected, timer c provides the variable-duty pulse output function. the output waveform differs depending on the contents of timer mode register c1 (tmc1: $00d) and timer write register c (twcl: $00e, twcu: $00f). registers for timer c operation: by using the following registers, timer c operation modes are selected and the timer c count is read and written. ? timer mode register c1 (tmc1: $00d) ? timer mode register c2 (tmc2: $014) ? timer write register c (twcl: $00e, twcu: $00f) ? timer read register c (trcl: $00e, trcu: $00f) timer mode register c1 (tmc1: $00d): four-bit write-only register that selects the free-running/ reload timer function, input clock source, and prescaler division ratio (figure 53). it is reset to $0 by mcu reset.
HD404459 series 69 the mode change of this register is valid from the second instruction execution cycle after the execution of the previous timer mode register c1 write instruction. setting timer c? initialization by writing to timer write register c (twcl: $00e, twcu: $00f) must be done after a mode change becomes valid. bit initial value read/write bit name 3 0 w tmc13 2 0 w tmc12 0 0 w tmc10 1 0 w tmc11 timer mode register c1 (tmc1: $00d) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 1024t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmc12 tmc10 tmc11 tmc13 0 1 free-running/reload timer selection free-running timer reload timer input clock period figure 53 timer mode register c1 (tmc1)
HD404459 series 70 timer mode register c2 (tmc2: $014): three-bit read/write register that selects the timer c output mode (figure 54). it is reset to $0 by mcu reset. bit initial value read/write bit name 3 not used 2 0 r/w tmc22 0 0 r/w tmc20 1 0 r/w tmc21 timer mode register c2 (tmc2: $014) tmc22 0 tmc21 r3 1 /toc mode selection r3 1 toc toc toc toc toc r3 1 port toggle output 0 output 1 output not used pwm output tmc20 0 1 0 1 0 1 0 1 0 1 10 1 figure 54 timer mode register c2 (tmc2) timer write register c (twcl: $00e, twcu: $00f): write-only register consisting of a lower digit (twcl) and an upper digit (twcu) (figures 55 and 56). the operation of timer write register c is basically the same as that of timer write register b (twbl: $00a, twbu: $00b). bit initial value read/write bit name 3 0 w twcl3 2 0 w twcl2 0 0 w twcl0 1 0 w twcl1 timer write register c (lower digit) (twcl: $00e) figure 55 timer write register c lower digit (twcl)
HD404459 series 71 bit initial value read/write bit name 3 undefined w twcu3 2 undefined w twcu2 0 undefined w twcu0 1 undefined w twcu1 timer write register c (upper digit) (twcu: $00f) figure 56 timer write register c upper digit (twcu) timer read register c (trcl: $00e, trcu: $00f): read-only register consisting of a lower digit (trcl) and an upper digit (trcu) that holds the count of the timer c upper digit(figures 57 and 58). the operation of timer read register c is basically the same as that of timer read register b (trbl: $00a, trbu:$00b). bit initial value read/write bit name 3 undefined r trcl3 2 undefined r trcl2 0 undefined r trcl0 1 undefined r trcl1 timer read register c (lower digit) (trcl: $00e) figure 57 timer read register c lower digit (trcl) bit initial value read/write bit name 3 undefined r trcu3 2 undefined r trcu2 0 undefined r trcu0 1 undefined r trcu1 timer read register c (upper digit) (trcu: $00f) figure 58 timer read register c upper digit(trcu) timer d timer d functions: timer d (figures 59 (a) and (b)) has the following functions. ? free-running/reload timer ? external event counter ? timer output operation (toggle, 0, 1, and pwm outputs) ? input capture timer
HD404459 series 72 timer d interrupt request flag (iftd) timer output control logic timer read register du (trdu) timer output control timer read register dl (trdl) clock timer counter d (tcd) selector system clock prescaler s (pss) overflow internal data bus timer write register du (twdu) timer write register dl (twdl) timer mode register d1 (tmd1) timer mode register d2 (tmd2) free-running/ reload control tod edge detection logic edge detection selection register 2 (esr2) edge detection control per 2 3 3 2 4 8 32 128 512 2048 evnd figure 59(a) block diagram of timer d (free-running/reload timer)
HD404459 series 73 selector 2 4 8 32 128 512 2048 3 2 per input capture status flag (icsf) input capture error flag (icef) timer d interrupt request flag (iftd) error control logic edge detection logic timer read register du (trdu) timer read register dl (trdl) read signal clock timer counter d (tcd) overflow system clock edge detection control prescaler s (pss) input capture timer control timer mode register d1 (tmd1) timer mode register d2 (tmd2) edge detection selection register 2 (esr2) evnd internal data bus figure 59(b) block diagram of timer d (input capture timer)
HD404459 series 74 timer d operations: free-running/reload timer operation: the free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register d1 (tmd1: $010). timer d is initialized to the value set in timer write register d (twdl: $011, twdu: $012) by software and incremented by one at each clock input. if an input clock is applied to timer d after it has reached $ff, an overflow is generated. in this case, if the reload timer function is enabled, timer d is initialized to its initial value set in timer write register d; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. the overflow sets the timer d interrupt request flag (iftd: $001, bit 2). iftd can be reset by software or mcu reset. refer to figure 3 and table 1 for details. external event counter operation: timer d is used as an external event counter by selecting the external event input as an input clock source. in this case, pin r4 0 /evnd must be set to evnd by port mode register c (pmrc: $025). either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (esr2: $027). when both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. timer d is incremented by one at each detection edge selected by detection edge select register 2 (esr2: $027). the other operation is basically the same as the free-running/reload timer operation. timer output operation: the following four output modes can be selected for timer d by setting timer mode register d2 (tmd2: $015). ? toggle ? 0 output ? 1 output ? pwm output by selecting the timer output mode, pin r3 2 /tod is set to tod. the output from tod is reset low by mcu reset. ? toggle output: the operation is basically the same as that of timer-b? toggle output. ? 0 output: the operation is basically the same as that of timer-b? 0 output. ? 1 output: the operation is basically the same as that of timer-b? 1 output. ? pwm output: the operation is basically the same as that of timer-c? pwm output. input capture timer operation: the input capture timer counts the clock cycles between trigger edges input to pin evnd. either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (esr2: $027).
HD404459 series 75 when a trigger edge is input to evnd, the count of timer d is written to timer read register d (trdl: $011, trdu: $012), and the timer d interrupt request flag (iftd: $001, bit 2) and the input capture status flag (icsf: $021, bit 0) are set. timer d is reset to $00, and then incremented again. while icsf is set, if a trigger input edge is applied to timer d, or if timer d generates an overflow, the input capture error flag (icef: $021, bit 1) is set. icsf and icef can be reset to 0 by mcu reset or by writing 0. by selecting the input capture operation, pin r3 2 /tod is set to r3 2 and timer d is reset to $00. registers for timer d operation: by using the following registers, timer d operation modes are selected and the timer d count is read and written. ? timer mode register d1 (tmd1: $010) ? timer mode register d2 (tmd2: $015) ? timer write register d (twdl: $011, twdu: $012) ? timer read register d (trdl: $011, trdu: $012) ? port mode register c (pmrc: $025) ? detection edge select register 2 (esr2: $027) timer mode register d1 (tmd1: $010): four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio (figure 60). it is reset to $0 by mcu reset. the mode change of this register is valid from the second instruction execution cycle after the execution of the previous timer mode register d1 (tmd1: $010) write instruction. setting timer d? initialization by writing to timer write register d (twdl: $011, twdu: $012) must be done after a mode change becomes valid. when selecting the input capture timer operation, select the internal clock as the input clock source.
HD404459 series 76 bit initial value read/write bit name 3 0 w tmd13 2 0 w tmd12 0 0 w tmd10 1 0 w tmd11 timer mode register d1 (tmd1: $010) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmd12 tmd10 tmd11 input clock period and input clock source r4 0 /evnd (external event input) tmd13 0 1 free-running/reload timer selection free-running timer reload timer figure 60 timer mode register d1 (tmd1)
HD404459 series 77 timer mode register d2 (tmd2: $015): four-bit read/write register that selects the timer d output mode and input capture operation (figure 61). it is reset to $0 by mcu reset. bit initial value read/write bit name 3 0 r/w tmd23 2 0 r/w tmd22 0 0 r/w tmd20 1 0 r/w tmd21 timer mode register d2 (tmd2: $015) tmd22 tmd20 0 1 0 1 0 1 0 1 tmd21 0 1 0 1 0 1 r3 2 /tod mode selection r3 2 tod tod tod tod tod r3 2 r3 2 port toggle output 0 output 1 output not used pwm output input capture (r3 2 port) tmd23 0 1 don't care don't care don't care figure 61 timer mode register d2(tmd2) timer write register d (twdl: $011, twdu: $012): write-only register consisting of a lower digit (twdl) and an upper digit (twdu) (figures 62 and 63). the operation of timer write register d is basically the same as that of timer write register b (twbl: $00a, twbu: $00b). bit initial value read/write bit name 3 0 w twdl3 2 0 w twdl2 0 0 w twdl0 1 0 w twdl1 timer write register d (lower digit) (twdl: $011) figure 62 timer write register d lower digit (twdl)
HD404459 series 78 bit initial value read/write bit name 3 undefined w twdu3 2 undefined w twdu2 0 undefined w twdu0 1 undefined w twdu1 timer write register d (upper digit) (twdu: $012) figure 63 timer write register d upper digit (twdu) timer read register d (trdl: $011, trdu: $012): read-only register consisting of a lower digit (trdl) and an upper digit (trdu) (figures 64 and 65). the operation of timer read register d is basically the same as that of timer read register b (trbl: $00a, trbu: $00b). when the input capture timer operation is selected and if the count of timer d is read after a trigger is input, either the lower or upper digit can be read first. bit initial value read/write bit name 3 undefined r trdl3 2 undefined r trdl2 0 undefined r trdl0 1 undefined r trdl1 timer read register d (lower digit) (trdl: $011) figure 64 timer read register d lower digit (trdl) bit initial value read/write bit name 3 undefined r trdu3 2 undefined r trdu2 0 undefined r trdu0 timer read register d (upper digit) (trdu: $012) 1 undefined r trdu1 figure 65 timer read register d upper digit (trdu) port mode register c (pmrc: $025): write-only register that selects r4 0 /evnd pin function (figure 51). it is reset to $0 by mcu reset.
HD404459 series 79 detection edge select register 2 (esr2: $027): write-only register that selects the detection edge of signals input to pin evnd (figure 66). it is reset to $0 by mcu reset. bit initial value read/write bit name 3 0 w esr23 2 0 w esr22 0 not used 1 not used detection edge register 2 (esr2: $027) esr23 0 1 esr22 0 1 0 1 evnd detection edge no detection falling-edge detection rising-edge detection double-edge detection * note: * both falling and rising edges are detected. figure 66 detection edge select register 2 (esr2)
HD404459 series 80 notes on use when using the timer output as pwm output, note the following point. from the update of the timer write register until the occurrence of the overflow interrupt, the pwm output differs from the period and duty settings, as shown in table 27. the pwm output should therefore not be used until after the overflow interrupt following the update of the timer write register. after the overflow, the pwm output will have the set period and duty cycle. table 27 pwm output following update of timer write register pwm output mode timer write register is updated during high pwm output timer write register is updated during low pwm output free running timer write register updated to value n interrupt request t (255 ?n) t (n + 1) timer write register updated to value n interrupt request t (n' + 1) t (255 ?n) t (n + 1) reload timer write register updated to value n interrupt request t t (255 ?n) t timer write register updated to value n interrupt request t t (255 ?n) t
HD404459 series 81 serial interface the mcu has a serial interface (figure 67). the serial interface serially transfers or receives 8-bit data, and includes the following features. multiple transmit clock sources ? external clock ? internal prescaler output clock ? system clock output level control in idle states five registers, an octal counter, and a multiplexer are also configured for the serial interface as follows. ? serial data register (srl: $006, sru: $007) ? serial mode register a (smra: $005) ? serial mode register b (smrb: $028) ? port mode register a (pmra: $004) ? miscellaneous register (mis: $00c) ? octal counter (oc) ? selector
HD404459 series 82 internal data bus ? 2 ? 8 ? 32 ? 128 ? 512 ? 2048 serial mode register b (smrb) sck selector system clock f per prescaler s (pss) idle controller 3 serial mode register a (smra) clock serial data register (sr) serial interrupt request flag (ifs) selector 1/2 1/2 si so octal counter (oc) i/o controller transfer control signal figure 67 serial interface block diagram serial interface operation selecting and changing the operating mode: to select an operating mode, use one of these combinations of port mode register a (pmra: $004) and serial mode register a (smra: $005) settings (table 28); to change the operating mode of the serial interface, always initialize the serial interface internally by writing data to serial mode register a. note that the serial interface is initialized by writing data to serial mode register a. refer to the following section, registers for serial interface, for details. pin setting: the r4 1 / sck pin is controlled by writing data to serial mode register a (smra: $005). pins r4 2 /si and r4 3 /so are controlled by writing data to port mode register a (pmra: $004). refer to the following section, registers for serial interface, for details. transmit clock source setting: the transmit clock source of the serial interface is set by writing data to serial mode register a (smra: $005) and serial mode register b (smrb: $028). refer to the following section, registers for serial interface, for details. data setting: transmit data of the serial interface is set by writing data to the serial data register (srl: $006, sru: $007). receive data of the serial interface is obtained by reading the contents of the serial data register. the serial data is shifted by each serial interface transmit clock and is input from or output to an external system.
HD404459 series 83 the output level of the so pins is undefined until the first data of each serial interface is output after mcu reset, or until the output level control in idle states is performed. transfer control: the serial interface is activated by the sts instruction. the octal counter is reset to 000 by the sts instruction and is incremented at the rising edge of the transmit clock for the serial interface. when the eighth transmit clock signal is input or when serial transmission/reception is discontinued, the octal counter is reset to 000, the serial interrupt request flag (ifs: $023, bit 0) for serial interface is set, and the transfer stops. when the prescaler output is selected as the transmit clock of the serial interface, the transmit clock frequency is selected as 4t cyc to 8192t cyc by setting bits 0 to 2 (smra0?mra2) of serial mode register a (smra: $005) and bit 0 (smrb0) of serial mode register b (smrb: $028) (table 29). table 28 serial interface operating mode smra pmra bit 3 bit 1 bit 0 operating mode 1 0 0 continuous clock output mode 1 transmit mode 1 0 receive mode 1 transmit/receive mode table 29 serial transmit clock (prescaler output) smrb smra bit 0 bit 2 bit 1 bit 0 prescaler division ratio transmit clock frequency 0000 ? 2048 4096t cyc 1 ? 512 1024t cyc 10 ? 128 256t cyc 1 ? 32 64t cyc 10 0 ? 8 16t cyc 1 ? 24t cyc 1000 ? 4096 8192t cyc 1 ? 1024 2048t cyc 10 ? 256 512t cyc 1 ? 64 128t cyc 10 0 ? 16 32t cyc 1 ? 48t cyc
HD404459 series 84 operating states: the serial interface has the following operating states, which allow transitions to occur between them (figure 68). ? sts wait state ? transmit clock wait state ? transfer state continuous clock output state (only in internal clock mode) sts wait state (octal counter = 000, transmit clock disabled) transmit clock wait state (octal counter = 000) transfer state (octal counter = 000) mcu reset 00 smra write 04 sts instruction 01 transmit clock 02 8 transmit clocks 03 sts instruction (ifs 1) 05 ? smra write (ifs 1) 06 ? external clock mode sts wait state (octal counter = 000, transmit clock disabled) transmit clock wait state (octal counter = 000) transfer state (octal counter = 000) smra write 14 sts instruction 11 transmit clock 12 15 sts instruction (ifs 1) ? 8 transmit clocks 13 internal clock mode continuous clock output state (pmra 0, 1 = 0, 0) smra write 18 transmit clock 17 16 note: refer to the operating states section for the explanations on the corresponding encircled numbers. mcu reset 10 ? smra write (ifs 1) figure 68 serial interface state transitions sts wait state: the serial interface enters sts wait state by mcu reset (00 and 10 in figure 68). in sts wait state, the serial interface is initialized and the transmit clock is ignored. if the sts instruction is then executed (01 and 11), the serial interface enters transmit clock wait state.
HD404459 series 85 transmit clock wait state: transmit clock wait state is the period between the sts execution and the falling edge of the first transmit clock. in transmit clock wait state, input of the transmit clock (02 and 12) increments the octal counter, shifts the serial data register (srl: $006, sru: $007), and enters the serial interface in transfer state. however, note that if continuous clock output state is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). the serial interface enters sts wait state by writing data to serial mode register a (smra: $005) (04 and 14) in transmit clock wait state. transfer state: transfer state is the period between the falling edge of the first clock and the rising edge of the eighth clock. in transfer state, the input of eight clocks or the execution of the sts instruction sets the octal counter to 000, and the serial interface enters another state. when the sts instruction is executed (05 and 15), transmit clock wait state is entered. when eight clocks are input, transmit clock wait state is entered (03) in external clock mode, or sts wait state is entered (13) in internal clock mode. in internal clock mode, the transmit clock stops after outputting eight clocks. in transfer state, writing data to serial mode register a (smra: $005) (06 and 16) initializes the serial interface, and sts wait state is entered. if the state changes from transfer to another state, the serial interrupt request flag (ifs: $023, bit 0) is set by the octal counter that is reset to 000. continuous clock output state (only in internal clock mode): continuous clock output state is entered only in internal clock mode. in this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the sck pin. when bits 0 and 1 (pmra0, pmra1) of port mode register a (pmra: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. if serial mode register a (smra: $005) is written to in continuous clock output mode (18), sts wait state is entered. output level control in idle states: when the serial interface is in sts instruction wait state and transmit clock wait state, the output of serial output pin so can be controlled by setting bit 1 (smrb1) of serial mode register b (smrb: $028) to 0 or 1. see figure 69 for an output level control example of the serial interface. note that the output level cannot be controlled in transfer state.
HD404459 series 86
state mcu reset pmra write smra write smrb write srl, sru write sts instruction sck pin (input) so pin ifs sts wait state transmit clock wait state transfer state transmit clock wait state sts wait state port selection external clock selection output level control in idle states dummy write for state transition output level control in idle states data write for transmission undefined lsb msb flag reset at transfer completion external clock mode state mcu reset pmra write smra write smrb write srl, sru write sts instruction sck pin (output) so pin ifs sts wait state transfer state transmit clock wait state sts wait state port selection internal clock selection output level control in idle states data write for transmission output level control in idle states undefined lsb msb flag reset at transfer completion internal clock mode figure 69 example of serial interface operation sequence
HD404459 series 87 transmit clock error detection (in external clock mode): the serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. a transmit clock error of this type can be detected (figure 70). if more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial interrupt request flag (ifs: $023, bit 0) is set, and transmit clock wait state is entered. at the falling edge of the next normal clock signal, the transfer state is again entered. after the transfer is completed and ifs is reset, writing to serial mode register a (smra: $005) then changes the state from transfer to sts wait. however, during the time the serial interface was in the transfer state with the serial interrupt request flag (ifs: $023, bit 0) being set again, the error can be detected. notes on use: initialization after writing to registers: if port mode register a (pmra: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode register a (smra: $005) again. serial interrupt request flag (ifs: $023, bit 0) set: for the serial interface, if the state is changed from transfer state to another by writing to serial mode register a (smra: $005) or executing the sts instruction during the first low pulse of the transmit clock, the serial interrupt request flag (ifs: $023, bit 0) is not set. to set the serial interrupt request flag (ifs: $023, bit 0), a serial mode register a (smra: $005) write or sts instruction execution must be programmed to be executed after confirming that the sck pin is at 1, that is, after executing the input instruction to port r4.
HD404459 series 88 transfer completion (ifs ? 1) interrupts inhibited ifs ? 0 smra write ifs = 1? transmit clock error processing normal termination yes no transmit clock error detection flowchart transmit clock error detection procedures state transmit clock wait state transfer state transfer state transmit clock wait state noise transfer state has been entered by the transmit clock error. when smra is written, ifs is set. flag set because octal counter reaches 000. flag reset at transfer completion. smra write 12 3 45678 sck pin (input) ifs figure 70 transmit clock error detection
HD404459 series 89 registers for serial interface the serial interface operation is selected, and serial data is read and written by the following registers. ? serial mode register a (smra: $005) ? serial mode register b (smrb: $028) ? serial data register (srl: $006, sru: $007) ? port mode register a (pmra: $004) ? miscellaneous register (mis: $00c) serial mode register a (smra: $005): this register has the following functions (figure 71). r4 1 / sck pin function selection transmit clock selection prescaler division ratio selection serial interface initialization serial mode register a (smra: $005) is a 4-bit write-only register. it is reset to $0 by mcu reset. a write signal input to serial mode register a (smra: $005) discontinues the input of the transmit clock to the serial data register (srl: $006, sru: $007) and octal counter, and the octal counter is reset to 000. therefore, if a write is performed during data transfer, the serial interrupt request flag (ifs: $023, bit 0) is set. written data is valid from the second instruction execution cycle after the write operation, so the sts instruction must be executed at least two cycles after that.
HD404459 series 90 bit initial value read/write bit name 3 0 w smra3 2 0 w smra2 0 0 w smra0 1 0 w smra1 serial mode register a (smra: $005) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 smra2 smra0 smra1 smra3 0 1 r4 1 / sck mode selection r4 1 sck sck output output input clock source prescaler system clock external clock prescaler division ratio refer to table 29 figure 71 serial mode register a (smra) serial mode register b (smrb: $028): this register has the following functions (figure 72). prescaler division ratio selection output level control in idle states serial mode register b (smrb: $028) is a 2-bit write-only register. it cannot be written during data transfer. by setting bit 0 (smrb0) of this register, the prescaler division ratio is selected. only bit 0 (smrb0) can be reset to 0 by mcu reset. by setting bit 1 (smrb1), the output level of the so pin is controlled in idle states of the serial interface. the output level changes at the same time that smrb1 is written to.
HD404459 series 91 bit initial value read/write bit name 3 not used 2 not used 0 0 w smrb0 1 undefined w smrb1 smrb0 0 1 serial clock division ratio prescaler output divided by 2 prescaler output divided by 4 serial mode register b (smrb: $028) smrb1 0 1 output level control in idle states low level high level figure 72 serial mode register b (smrb) serial data register (srl: $006, sru: $007): this register has the following functions (figures 73 and 74). transmission data write and shift receive data shift and read writing data in this register is output from the so pin, lsb first, synchronously with the falling edge of the transmit clock (figure 75); data is input, lsb first, through the si pin at the rising edge of the transmit clock. data cannot be read or written during serial data transfer. if a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed. bit initial value read/write bit name 3 undefined r/w sr3 2 undefined r/w sr2 0 undefined r/w sr0 1 undefined r/w sr1 serial data register (lower digit) (srl: $006) figure 73 serial data register lower digit (srl)
HD404459 series 92 bit initial value read/write bit name 3 undefined r/w sr7 2 undefined r/w sr6 0 undefined r/w sr4 1 undefined r/w sr5 serial data register (upper digit) (sru: $007) figure 74 serial data register upper digit (sru) lsb msb 12 345 678 transmit clock serial output data serial input data latch timing figure 75 serial interface output timing
HD404459 series 93 port mode register a (pmra: $004): this register has the following functions (figure 76). r4 2 /si pin function selection r4 3 /so pin function selection port mode register a (pmra: $004) is a 2-bit write-only register, and is reset to $0 by mcu reset. bit initial value read/write bit name 3 not used 2 not used 0 0 w pmra0 1 0 w pmra1 port mode register a (pmra: $004) pmra0 0 1 r4 3 /so mode selection r4 3 so pmra1 0 1 r4 2 /si mode selection r4 2 si figure 76 port mode register a (pmra)
HD404459 series 94 miscellaneous register (mis: $00c): this register has the following functions (figure 77). r4 3 /so pin pmos control miscellaneous register (mis: $00c) is a 4-bit write-only register and is reset to $0 by mcu reset. bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 miscellaneous register (mis: $00c) mis1 mis0 0 1 0 1 t rc 0.12207 ms 7.8125 ms 62.5 ms not used mis2 0 1 r4 3 /so pmos on/off selection on off mis3 0 1 pull-up mos on/off selection off on 0 1 figure 77 miscellaneous register (mis)
HD404459 series 95 comparator the comparator (figure 78) compares an analog input voltage with a reference voltage. either a 16-level internal or external reference power supply can be selected. the voltage comparison is started by writing 1 to the comparator start flag (cmsf: $020, bit 2), and is completed after 4t cyc . the comparison result is stored into bit 3 (cer: $017, bit 3) of the comparator enable register, and can be read by the bit test instruction (tm or tmd). the comparison result must be read after confirming that the comparator start flag (cmsf: $020, bit 2) is at 0 (figure 79). comp comparator control register (ccr) comparator start flag (cmsf) comparator enable register (cer) internal data bus r9 3 /vc ref ra 0 /comp 0 ra 1 /comp 1 ra 2 /comp 2 ra 3 /comp 3 4 4 1 1 1 1 3 2 selector selector selector figure 78 block diagram of comparator
HD404459 series 96 4t cyc (ra port must not be used) comparator start flag write cycle internal system clock comparator start flag (cmsf) voltage comparison result (cer3) figure 79 comparator operation timing
HD404459 series 97 comparator control register (ccr: $016): four-bit write-only register which selects a 16-level internal reference power supply (figure 80). the comparator control register (ccr: $016) is reset to $0 by mcu reset. bit initial value read/write bit name 3 0 w ccr3 2 0 w ccr2 0 0 w ccr0 1 0 w ccr1 comparator control register (ccr: $016) ccr0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 reference power supply selection 1/17 v cc 2/17 v cc 3/17 v cc 4/17 v cc 5/17 v cc 6/17 v cc 7/17 v cc 8/17 v cc 9/17 v cc 10/17 v cc 11/17 v cc 12/17 v cc 13/17 v cc 14/17 v cc 15/17 v cc 16/17 v cc ccr1 0 1 0 1 0 1 0 1 ccr2 0 1 0 1 ccr3 0 1 figure 80 comparator control register (ccr) comparator enable register (cer: $017): this register consists of a 3-bit write-only register and a 1-bit read-only register. it selects the analog input pins and reference voltage, and indicates the voltage comparison result. the comparison result output is 0 when an analog input voltage is lower than the reference voltage, and is 1 when an analog input voltage is higher than the reference voltage. the comparison result is read by the bit test instruction (tm or tmd). the comparator enable register (cer: $017) is reset to $0 by mcu reset.
HD404459 series 98 bit initial value read/write bit name 3 0 r cer3 2 0 w cer2 0 0 w cer0 1 0 w cer1 comparator enable register (cer: $017) cer1 0 1 analog input mode selection comp 0 comp 1 comp 2 comp 3 cer2 0 1 external reference power supply internal reference power supply cer0 0 1 0 1 cer3 voltage comparison result analog input voltage is lower than reference voltage analog input voltage is higher than reference voltage 0 1 reference power supply selection figure 81 comparator enable register (cer) comparator start flag (cmsf: $020, bit 2): starts the comparator operation. the comparator starts the voltage comparison by writing 1 to the comparator start flag (cmsf: $020, bit 2), and automatically completes the voltage comparison after 4t cyc . the comparator start flag is then reset to 0. the comparison result must be read after confirming that the comparator start flag is at 0. the comparator start flag is reset to 0 by mcu reset. notes on use : ra 0 /comp 0 ?a 3 /comp 3 pins are used only for the comparator during voltage comparison. these pins cannot be used for r ports. the comparator operates only in the active and standby modes. the switch for the internal power supply is turned on when the internal power supply is selected. the switch is turned off except in active and standby modes. when the external power supply is used for a reference voltage, r9 3 /vc ref must not be used as an r port.
HD404459 series 99 notes on mounting assemble all parts including the hd404458/HD404459 on a board, noting the points described below. between the v cc and gnd lines, connect capacitors designed for use in ordinary power supply circuits. an example connection is described in figure 82. no resistors can be inserted in series in the power supply circuit, so the capacitors should be connected in parallel. the capacitors are a large capacitance c 1 and a small capacitance c 2 . v gnd cc v gnd cc c 1 c 2 figure 82 example of connections
HD404459 series 100 programmable rom (hd4074459) the hd4074459 is a ztat tm microcomputer with a built-in prom that can be programmed in prom mode. prom mode pin description pin no. mcu mode prom mode pin no. mcu mode prom mode fp-64a pin name i/o pin name i/o fp-64a pin name i/o pin name i/o 1ra 0 /comp 0 i29r1 0 i/o a 5 i 2ra 1 /comp 1 i30r1 1 i/o a 6 i 3ra 2 /comp 2 i31r1 2 i/o a 7 i 4ra 3 /comp 3 i32r1 3 i/o a 8 i 5 test i test i33 r2 0 i/o a 0 i 6 osc 1 iv cc 34 r2 1 i/o a 10 i 7 osc 2 o35r2 2 i/o a 11 i 8 gnd gnd 36 r2 3 i/o a 12 i 9 x2 o 37 r3 0 /tob i/o 10 x1 i gnd 38 r3 1 /toc i/o 11 reset i reset i 39 r3 2 /tod i/o 12 d 0 i/o o 0 i/o 40 r3 3 / evnb i/o 13 d 1 i/o o 1 i/o 41 r4 0 /evnd i/o 14 d 2 i/o o 2 i/o 42 r4 1 / sck i/o 15 d 3 i/o o 3 i/o 43 r4 2 /si i/o 16 d 4 i/o o 4 i/o 44 r4 3 /so i/o 17 d 5 i/o o 5 i/o 45 r5 0 /( wu 0 ) i/o 18 d 6 i/o o 6 i/o 46 r5 1 /( wu 1 ) i/o 19 d 7 i/o o 7 i/o 47 r5 2 /( wu 2 ) i/o 20 d 8 i/o a 13 i48 r5 3 /( wu 3 ) i/o 21 d 9 i/o a 14 i49 r6 0 /( wu 4 ) i/o ce i 22 d 10 iv pp i50 r6 1 /( wu 5 ) i/o oe i 23 d 11 / stopc ia 9 i51 r6 2 /( wu 6 ) i/o v cc 24 v cc ? cc 52 r6 3 /( wu 7 ) i/o v cc 25 r0 0 / int 0 i/o m 0 i53 r7 0 i/o a 1 i 26 r0 1 / int 1 i/o m 1 i54 r7 1 i/o a 2 i 27 r0 2 /int 2 i/o 55 r7 2 i/o a 3 i 28 r0 3 /int 3 i/o 56 r7 3 i/o a 4 i
HD404459 series 101 pin no. mcu mode prom mode pin no. mcu mode prom mode fp-64a pin name i/o pin name i/o fp-64a pin name i/o pin name i/o 57 r8 0 i/o o 4 i/o 61 r9 0 i/o o 0 i/o 58 r8 1 i/o o 3 i/o 62 r9 1 i/o v cc 59 r8 2 i/o o 2 i/o 63 r9 2 i/o 60 r8 3 i/o o 1 i/o 64 r9 3 /vc ref i notes: 1. i/o: input/output pin, i: input pin, o: output pin 2. each of o 0 ? 4 has two pins; before using them, each pair must be connected together.
HD404459 series 102 programming the built-in prom the mcu? built-in prom is programmed in prom mode. this prom mode is set by pulling test , m 0 , and m 1 low, and reset high (figure 83). in prom mode, the mcu does not operate, but it can be programmed in the same way as any other commercial 27256-type eprom using a standard prom programmer and a 64-to-28-pin socket adapter. refer to table 31 for the recommended prom programmers and socket adapters of the hd4074459. since an hmcs400-series instruction is ten bits long, the hmcs400-series mcu has a built-in conversion circuit to enable the use of a general-purpose prom programmer. this circuit splits each instruction into five lower bits and five upper bits that are read from or written to consecutive addresses. this means that if, for example, 16 kwords of built-in prom are to be programmed by a general-purpose prom programmer, a 32-kbyte address space ($0000?7fff) must be specified. warnings 1. always specify addresses $0000 to $7fff when programming with a prom programmer. if address $8000 or higher is accessed, the prom may not be programmed or verified correctly. set all data in unused addresses to $ff. note that the plastic-package versions cannot be erased or reprogrammed. 2. make sure that the prom programmer, socket adapter, and lsi are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the lsi. before starting programming, make sure that the lsi is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the programmer. 3. prom programmers have two voltages (v pp ): 12.5 v and 21 v. remember that ztat tm devices require a v pp of 12.5 v?he 21-v setting will damage them. 12.5 v is the intel 27256 setting. programming and verification the built-in prom of the mcu can be program med at high speed without risk of voltage stress or damage to data reliability. refer to table 30 for programming and verification modes. for details of prom programming, refer to the preface section, notes on prom programming. table 30 prom mode selection pin mode ce oe v pp o 0 ? 7 programming low high v pp data input verification high low v pp data output programming inhibited high high v pp high impedance
HD404459 series 103 table 31 recommended prom programmers and socket adapters prom programmer socket adapter manufacturer model name package model name manufacturer data i/o corp. 121b fp-64a hs4459esh01h hitachi aval corp. pkw-1000 fp-64a hs4459esh01h hitachi address a 0 to a 14 data o 0 to o 7 oe ce v cc v pp gnd v cc v cc o 0 to o 7 a 0 to a 14 oe ce v pp reset test m 0 m 1 v cc osc 1 r6 2 r6 3 r9 1 x1 hd4074459h figure 83 prom mode connections
HD404459 series 104 addressing modes ram addressing modes the mcu has three ram addressing modes (figure 84). register indirect addressing mode: the contents of the w, x, and y registers (10 bits in total) are used for ram addressing. direct addressing mode: a direct addressing instruction consists of two words. the first word contains the opcode, and the contents of the second word (10 bits) are used for ram addressing. memory register addressing mode: the memory registers (mr), which are located in 16 addresses from $040 to $04f, are accessed with the lamr and xmra instructions. ap 9 ap 0 w 1 y 0 w register x register y register ram address register indirect addressing ap 9 ap 0 ram address direct addressing d 9 d 0 2nd word of instruction opcode 1st word of instruction ap 9 ap 0 ram address memory register addressing m 3 opcode instruction 000100 ap 8 ap 7 ap ap 5 ap 4 6 ap 3 ap 2 ap 1 ap ap ap ap ap ap ap ap 87654321 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 ap 8 ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 w 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 m 2 m 1 m 0 figure 84 ram addressing modes
HD404459 series 105 rom addressing modes and the p instruction the mcu has four rom addressing modes (figure 85). direct addressing mode: a program can branch to any address in rom memory space by executing the jmpl, brl, or call instruction. each of these instructions replaces the 14 program counter bits (pc 13 pc 0 ) with 14-bit immediate data. current page addressing mode: the mcu has 64 pages of rom with 256 words per page. a program can branch to any address in the current page by executing the br instruction. this instruction replaces the eight low-order bits of the program counter (pc 7 ?c 0 ) with eight-bit immediate data. if the br instruction is on a page boundary (address 256n + 255), executing that instruction transfers the pc contents to the next physical page (figure 87). this means that the execution of the br instruction on a page boundary will make the program branch to the next page. note that the hmcs400-series cross macroassembler has an automatic paging feature for rom pages. zero-page addressing mode: a program can branch to the zero-page subroutine area located at $0000 $003f by executing the cal instruction. when the cal instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (pc 5 ?c 0 ), and 0s are placed in the eight high- order bits (pc 13 ?c 6 ). table data addressing mode: a program can branch to an address determined by the contents of four-bit immediate data, the accumulator, and the b register by executing the tbr instruction. p instruction: rom data addressed in table data addressing mode can be referenced with the p instruction (figure 86). if bit 8 of the rom data is 1, eight bits of rom data are written to the accumulator and the b register. if bit 9 is 1, eight bits of rom data are written to the r1 and r2 port output registers. if both bits 8 and 9 are 1, rom data is written to the accumulator and the b register, and also to the r1 and r2 port output registers at the same time. the p instruction has no effect on the program counter.
HD404459 series 106 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 2nd word of instruction opcode 1st word of instruction [jmpl] [brl] [call] pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc pc pc pc 10 11 12 13 program counter direct addressing zero page addressing a 5 a 4 a 3 a 2 a 1 a 0 instruction [cal] opcode pc 98 pc 76 pc 54 pc 3 pc 1 pc 0 pc pc 10 11 12 13 program counter 00 00 0 0 0 0 pc pc pc pc pc pc 2 b 1 b 0 a 3 a 2 a 1 a 0 accumulator program counter table data addressing pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc pc pc 10 11 12 13 b 2 b 3 b register p 3 p 0 [tbr] instruction opcode 0 0 p 2 p 1 pc opcode b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 instruction pc 90 pc pc pc 11 12 13 program counter current page addressing [br] pc 10 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc pc 8 pc p 0 p 1 p 2 p 3 figure 85 rom addressing modes
HD404459 series 107 b 1 b 0 a 3 a 2 a 1 a 0 accumulator referenced rom address address designation ra 9 ra 8 ra 7 ra 6 ra 5 ra 4 ra 3 ra 2 ra 1 ra 0 ra ra ra 10 11 12 13 b 2 b 3 b register 0 0 p 3 p 0 [p] instruction opcode p 2 p 1 ra ro 9 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 bbbb aa a a 3210 3210 if ro = 1 8 accumulator, b register rom data pattern output ro 9 rom data r2 32103210 if ro = 1 9 output registers r1, r2 r2 r2 r2 r1 r1 r1 r1 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 figure 86 p instruction br aaa aaa nop 256 (n ?1) + 255 256n br aaa br bbb 256n + 254 256n + 255 256 (n + 1) bbb nop figure 87 branching when the branch destination is on a page boundary
HD404459 series 108 absolute maximum ratings (hd404458/HD404459) item symbol value unit notes supply voltage v cc ?.3 to +4.0 v pin voltage v t ?.3 to (v cc + 0.3) v total permissible input current ? i o 50 ma 2 total permissible output current ? i o 50 ma 3 maximum input current i o 4 ma 4, 5 maximum output current ? o 4 ma 5, 6 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +125 c absolute maximum ratings (hd4074459) item symbol value unit notes supply voltage v cc ?.3 to +4.0 v programming voltage v pp ?.3 to +14.0 v 1 pin voltage v t ?.3 to (v cc + 0.3) v total permissible input current ? i o 50 ma 2 total permissible output current ? i o 50 ma 3 maximum input current i o 4 ma 4, 5 maximum output current ? o 4 ma 5, 6 operating temperature t opr ?0 to +75 c7 storage temperature t stg ?5 to +125 c notes: permanent damage may occur if these absolute maximum ratings are exceeded. normal operation must be under the conditions stated in the electrical characteristics tables. if these conditions are exceeded, the lsi may malfunction or its reliability may be affected. 1. applies to d 10 (v pp ) of the hd4074459. 2. the total permissible input current is the total of input currents simultaneously flowing in from all the i/o pins to ground. 3. the total permissible output current is the total of output currents simultaneously flowing out from v cc to all i/o pins. 4. the maximum input current is the maximum current flowing from each i/o pin to ground. 5. applies to d 0 ? 9 , r0?8, and r9 0 ?9 2 . 6. the maximum output current is the maximum current flowing out from v cc to each i/o pin. 7. depends on the supply voltage.
HD404459 series 109 electrical characteristics dc characteristics hd404458, HD404459: v cc = 1.8 to 3.6 v, gnd = 0 v, t a = ?0 to +75 c, f osc = 0.4 to 4.0 mhz hd4074459: v cc = 2.2 to 2.7 v, gnd = 0 v, t a = ? to +60 c, f osc = 0.4 to 2.0 mhz; v cc = 2.7 to 3.6 v, gnd = 0 v, t a = ?0 to +75 c, f osc = 0.4 to 4.0 mhz, unless otherwise specified. item symbol pin(s) min typ max unit test condition notes input high voltage v ih reset, stopc , int 0 , int 1 , int 2 , int 3 , sck , si, wu 0 wu 7 , evnb , evnd 0.9v cc ? cc + 0.3 v osc 1 v cc ?0.3 v cc + 0.3 v external clock operation input low voltage v il reset, stopc , int 0 , int 1 , int 2 , int 3 , sck , si, wu 0 wu 7 , evnb , evnd ?.3 0.1v cc v osc 1 ?.3 0.3 v external clock operation output high voltage v oh sck , so, tob, toc, tod v cc ?0.5 v i oh = 0.3 ma output low voltage v ol sck , so, tob, toc, tod 0.4 v i ol = 0.4 ma i/o leakage current | i il | reset, stopc , int 0 , int 1 , int 2 , int 3 , sck , si, wu 0 wu 7 , so, evnb , evnd, osc 1 , tob, toc, tod 1.0 m av in = 0 v to v cc 1 current dissipation in active mode i cc v cc 3 6 ma hd404458, HD404459: v cc = 3.0 v, f osc = 4 mhz 2 5 9 ma hd4074459: v cc = 3.0 v, f osc = 4 mhz 2
HD404459 series 110 item symbol pin(s) min typ max unit test condition notes current dissipation in standby mode i sby v cc 1.2 3 ma v cc = 3.0 v, f osc = 4 mhz 3 current dissipation in subactive mode i sub v cc ?570 m a hd404458, HD404459: v cc = 3.0 v, 32-khz oscillator 70 150 m a hd4074459: v cc = 3.0 v, 32-khz oscillator current dissipation in watch mode i wtc v cc ?15 m av cc = 3.0 v, 32-khz oscillator 4 current dissipation in stop mode i stop v cc ?10 m av cc = 3.0 v, no 32-khz oscillator 4 stop mode retaining voltage v stop v cc 1.5 v no 32-khz oscillator 5 notes: 1. output buffer current is excluded. 2. i cc is the source current when no i/o current is flowing while the mcu is in reset state. test conditions: mcu: reset pins: reset at v cc (0.9v cc to v cc ) test at v cc (0.9v cc to v cc ) 3. i sby is the source current when no i/o current is flowing while the mcu timer is operating. test conditions: mcu: i/o reset serial interface stopped standby mode pins: reset at gnd (0 v to 0.3 v) test at v cc (0.9v cc to v cc ) 4. these are the source currents when no i/o current is flowing. test conditions: pins: reset at gnd (0 v to 0.3 v) test at v cc (0.9v cc to v cc ) d 10 * at v cc (0.9v cc to v cc ) note: * applies to hd4074459 5. ram data retention is the voltage required for retaining ram data.
HD404459 series 111 i/o characteristics for standard pins hd404458, HD404459: v cc = 1.8 to 3.6 v, gnd = 0 v, t a = ?0 to +75 c, f osc = 0.4 to 4.0 mhz hd4074459: v cc = 2.2 to 2.7 v, gnd = 0 v, t a = ? to +60 c, f osc = 0.4 to 2.0 mhz; v cc = 2.7 to 3.6 v, gnd = 0 v, t a = ?0 to +75 c, f osc = 0.4 to 4.0 mhz, unless otherwise specified. item symbol pin(s) min typ max unit test condition note input high voltage v ih d 0 ? 11 , r0?a 0.7v cc ? cc + 0.3 v input low voltage v il d 0 ? 11 , r0?a ?.3 0.3v cc v output high voltage v oh d 0 ? 9 , r0?8, r9 0 ?9 2 v cc ?0.5 v i oh = 0.3 ma output low voltage v ol d 0 ? 9 , r0?8, r9 0 ?9 2 0.4 v i ol = 0.4 ma i/o leakage current | i il |d 0 ? 11 , r0?a 1 m a hd404458, HD404459: v in = 0 v to v cc 1 d 0 ? 9 , d 11 , r0?a 1 m a hd4074459: v in = 0 v to v cc 1 d 10 1 m a hd4074459: v in = v cc ?0.3 to v cc 1 20 m a hd4074459: v in = 0 v to 0.3 v 1 pull-up mos current ? pu d 0 ? 9 , r0?8, r9 0 ?9 2 54090 m av cc = 3.0 v, v in = 0 v note: 1. output buffer current is excluded.
HD404459 series 112 voltage comparator characteristics hd404458, HD404459: v cc = 2.0 to 3.6 v, gnd = 0 v, t a = ?0 to +75 c, f osc = 0.4 to 4.0 mhz hd4074459: v cc = 2.2 to 2.7 v, gnd = 0 v, t a = ? to +60 c, f osc = 0.4 to 2.0 mhz; v cc = 2.7 to 3.6 v, gnd = 0 v, t a = ?0 to +75 c, f osc = 0.4 to 4.0 mhz,unless otherwise specified. item symbol pin(s) min typ max unit test condition note input high voltage v iha comp 0 comp 3 v ref + 0.17 v 1 input low voltage v ila comp 0 comp 3 v ref ?0.03 v 1 analog input standard voltage range vc ref vc ref 0v cc v note: 1. when an internal reference voltage is selected, the standard voltage is an expected voltage of internal v ref specified by the comparator control register (ccr).
HD404459 series 113 ac characteristics hd404458, HD404459: v cc = 1.8 to 3.6 v, gnd = 0 v, t a = ?0 to +75 c, f osc = 0.4 to 4.0 mhz hd4074459: v cc = 2.2 to 2.7 v, gnd = 0 v, t a = ? to +60 c, f osc = 0.4 to 2.0 mhz; v cc = 2.7 to 3.6 v, gnd = 0 v, t a = ?0 to +75 c, f osc = 0.4 to 4.0 mhz, unless otherwise specified. item symbol pin(s) min typ max unit test condition notes clock oscillation frequency f osc osc 1 , osc 2 0.4 4.0 mhz hd404458, HD404459: 1/4division, v cc = 1.8 v to 3.6 v hd4074459: 1/4 division, v cc = 2.7 v to 3.6 v 0.4 2.0 mhz hd4074459: 1/4 division, v cc = 2.2 v to 2.7 v x1, x2 32.768 khz instruction cycle time t cyc 1.0 10 m s hd404458, HD404459: 1/4 division, v cc = 1.8 v to 3.6 v hd4074459: 1/4 division, v cc = 2.7 v to 3.6 v 2.0 10 m s hd4074459: 1/4 division, v cc = 2.2 v to 2.7 v t subcyc 244.14 m s 32-khz oscillator, 1/8 division 122.07 m s 32-khz oscillator, 1/4 division oscillation stabilization time (ceramic oscillator) t rc osc 1 , osc 2 60 ms 1 oscillation stabilization time (crystal oscillator) t rc osc 1 , osc 2 60 ms 1 x1, x2 3 s t a = ?0 c to+60 c2 external clock high width t cph osc 1 105 ns f osc = 4 mhz 3 external clock low width t cpl osc 1 105 ns f osc = 4 mhz 3
HD404459 series 114 item symbol pin(s) min typ max unit test condition notes external clock rise time t cpr osc 1 20 ns 3 external clock fall time t cpf osc 1 20 ns 3 int 0 ?nt 3 , evnb , wu 0 wu 7 , evnd high widths t ih int 0 ?nt 3 , wu 0 wu 7 , evnb , evnd 2 t cyc / t subcyc 4, 7 int 0 ?nt 3 , evnb , wu 0 wu 7 , evnd low widths t il int 0 ?nt 3 , wu 0 wu 7 , evnb , evnd 2 t cyc / t subcyc 4, 7 reset high width t rsth reset 2 t cyc ? stopc low width t stpl stopc 1 t rc ? reset fall time t rstf reset 20 ms 5 stopc rise time t stpr stopc 20 ms 6 input capacitance c in all pins except for d 10 15 pf f = 1 mhz, v in = 0 v d 10 15 pf hd404458, HD404459: f = 1mhz, v in = 0 v 180 pf hd4074459: f = 1 mhz, v in = 0 v notes: 1. the oscillation stabilization time is the period required for the oscillator to stabilize after v cc reaches 1.8 v (2.2 v: hd4074459) at power-on, or after reset input goes high or stopc input goes low when stop mode is cancelled. at power-on or when stop mode is cancelled, reset or stopc must be input for at least t rc to ensure the oscillation stabilization time. if using a ceramic or crystal oscillator, contact its manufacturer to determine the required stabilization time, since it will depend on the circuit constants and stray capacitances. set bits 0 and 1 (mis0, mis1) of the miscellaneous register (mis: $00c) according to the oscillation stabilization time of the system oscillation. 2. the oscillation stabilization time is the period required for the oscillator to stabilize after v cc reaches 1.8 v (2.2 v: hd4074459) at power-on, or after reset input goes high or stopc input goes low when stop mode is cancelled. if using a crystal oscillator, contact its manufacturer to determine the required stabilization time, since it will depend on the circuit constants and stray capacitances. 3. refer to figure 88. 4. refer to figure 89. the t cyc unit applies when the mcu is in standby or active mode. the t subcyc unit applies when the mcu is in watch or subactive mode. 5. refer to figure 90. 6. refer to figure 91. 7. in watch or subactive mode, the periods when the int 0 and wu 0 wu 7 signals are high and when these signals are low must be equal to the interrupt frame period or longer.
HD404459 series 115 serial interface timing characteristics hd404458, HD404459: v cc = 1.8 to 3.6 v, gnd = 0 v, t a = ?0 to +75 c, f osc = 0.4 to 4.0 mhz hd4074459: v cc = 2.2 to 2.7 v, gnd = 0 v, t a = ? to +60 c, f osc = 0.4 to 2.0 mhz; v cc = 2.7 to 3.6 v, gnd = 0 v, t a = ?0 to +75 c, f osc = 0.4 to 4.0 mhz, unless otherwise specified. during transmit clock output item symbol pin min typ max unit test condition note transmit clock cycle time t scyc sck 1.0 t cyc load shown in figure 93 1 transmit clock high width t sckh sck 0.4 t scyc load shown in figure 93 1 transmit clock low width t sckl sck 0.4 t scyc load shown in figure 93 1 transmit clock rise time t sckr sck 200 ns load shown in figure 93 1 transmit clock fall time t sckf sck 200 ns load shown in figure 93 1 serial output data delay time t dso so 500 ns load shown in figure 93 1 serial input data setup time t ssi si 300 ns 1 serial input data hold time t hsi si 300 ns 1 note: 1. refer to figure 92. during transmit clock input item symbol pin min typ max unit test condition note transmit clock cycle time t scyc sck 1.0 t cyc ? transmit clock high width t sckh sck 0.4 t scyc ? transmit clock low width t sckl sck 0.4 t scyc ? transmit clock rise time t sckr sck 200 ns 1 transmit clock fall time t sckf sck 200 ns 1 serial output data delay time t dso so 500 ns load shown in figure 93 1 serial input data setup time t ssi si 300 ns 1 serial input data hold time t hsi si 300 ns 1 note: 1. refer to figure 92.
HD404459 series 116 osc 1 1/f cp t cpl t cpf t cph t cpr v cc ?0.3 v 0.3 v figure 88 external clock timing t il 0.9v cc 0.1v cc t ih wu 0 to wu 7 , int 0 to int 3 , evnb , evnd figure 89 interrupt timing 0.1v cc 0.9v cc t rsth t rstf reset figure 90 reset timing
HD404459 series 117 0.1v cc 0.9v cc t stpl t stpr stopc figure 91 stopc timing 0.9v cc 0.1v cc t dso t sckf t sckl t ssi t hsi t scyc t sckr 0.4 v v ?0.5 v cc v ?0.5 v (0.9v ) * cc 0.4 v (0.1v ) * sck so si note: * v cc ?0.5 v and 0.4 v are the threshold voltages for transmit clock output, and 0.9v cc and 0.1v cc are the threshold voltages for transmit clock input. cc cc t sckh figure 92 serial interface timing r l = 2.6 k w v cc 1s2074 h or equivalent r = 12 k w test point c = 30 pf figure 93 timing load circuit
HD404459 series 118 notes on rom out please pay attention to the following items regarding rom out. on rom out, fill the rom area indicated below with 1s to create the same data size as a 16-kword version (HD404459). a 16-kword data size is required to change rom data to mask manufacturing data since the program used is for a 16-kword version. this limitation applies when using an eprom or a data base. vector address zero-page subroutine (64 words) pattern & program (8,192 words) not used rom 8-kword version: hd404458 address $2000?3fff $0000 $000f $0010 $003f $0040 $1fff $2000 $3fff fill this area with 1s
HD404459 series 119 hd404458, HD404459 option list please check off the appropriate applications and enter the necessary information. 3. rom code media date of order customer department name rom code name lsi number eprom: ceramic oscillator crystal oscillator external clock f = mhz f = mhz f = mhz 4. oscillator for osc1 and osc2 the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu...). eprom: the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms. hd404458 HD404459 8-kword 16-kword 1. rom size fp-64a 6. package please specify the first type listed below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat version). used not used 5. stop mode with 32-khz cpu operation, with time-base for clock without 32-khz cpu operation, with time-base for clock without 32-khz cpu operation, without time-base 2. optional functions note: * options marked with an asterisk require a subsystem crystal oscillator (x1, x2). * *
HD404459 series 120 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

▲Up To Search▲

Price & Availability of HD404459

	To Download HD404459 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .